Z86E3016PSG Datasheet, PDF (161/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
143
Mn
M1
M2
T1 T2 T3 T1 T2 T3 T1 T2 T3
Interrupt Request
Sampled Internally
External Interrupt
Request Sampled
Figure 95. Interrupt Request Timing
Interrupt Initialization
After reset, all interrupts are disabled and must be initialized before vec-
tored or polled interrupt processing can begin. The Interrupt Priority Reg-
ister (IPR), Interrupt Mask Register (IMR), and Interrupt Request
Register (IRQ) must be initialized, in that order, to start the interrupt pro-
cess.
Interrupt Priority Register Initialization
The Interrupt Priority Register (IPR) shown in Figure 96 is a write-only
register that sets priorities for the vectored interrupts in order to resolve
simultaneous interrupt requests. (There are 48 sequence possibilities for
interrupts.) The six interrupt levels IRQ0-IRQ5 are divided into three
groups of two interrupt requests each. One group contains IRQ3 and
IRQ5. The second group contains IRQ0 and IRQ2, while the third group
contains IRQ1 and IRQ4.
Priorities can be set both within and between groups as shown in
Tables 19 and 20. Bits 1, 2, and 5 define the priority of the individual
members within the three groups. Bits 0, 3, and 4 are encoded to define
six priority orders between the three groups. Bits 6 and 7 are reserved.
UM001602-0904
Interrupts