Z86E3016PSG Datasheet, PDF(139/348 Page) Zilog, Inc. – Z86E3016PSG

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Z86E3016PSG Datasheet, PDF (139/348 Pages) Zilog, Inc. – Z86E3016PSG

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Z8 CPU

User Manual

121

be set to 1. Counting actually starts when the Enable Count bit is written

by an instruction. The ï¬rst decrement occurs four internal clock periods

after the Enable Count bit has been set. If T1 is conï¬gured to use an exter-

nal clock, the ï¬rst decrement begins on the next clock period. The Load

and Enable Count bits can be set at the same time. For example, using the

instruction:

OR TMR,#03h

sets both D0 and D1 of the TMR. This loads the initial values of PRE0

and T0 into their respective counters and starts the count after the M2T2

machine state after the operand is fetched (see Figure 74).

R243 PRE1

Prescaler 1 Register

(% F3; Write-Only)

R245 PRE0

Prescaler 0 Register

(% F5; Write-Only)

D0

Count Mode

0 = T1 Single Pass

1 = T1 Modulo-n

Figure 74. Starting The Count

UM001602-0904

Counters and Timers

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