Z86E3016PSG Datasheet, PDF (197/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
179
If the associated IRQ3 is enabled, an interrupt is generated. Bit 5 controls
the clock phase of the SPI. A 1 in bit 5 allows for receiving data on the
clock’s falling edge and transmitting data on the clock’s rising edge. A 0
allows receiving data on the clock’s rising edge and transmitting on the
clock’s falling edge. The SPI clock source is defined in bit 6. A 1 uses
Timer0 output for the SPI clock, and a 0 uses TCLK for clocking the SPI.
Finally, bit 7 determines whether the SPI is used as a Master or a Slave. A
1 puts the SPI into Master mode and a 0 puts the SPI into Slave mode.
SPI Operation
The SPI is used in one of two modes: either as system slave, or as system
master. Several of the possible system configurations are shown in
Figure 117. In slave mode, data transfer starts when the slave select (SS)
pin goes active. Data is transferred into the slave’s SPI Shift Register
through the DI pin, which has the same address as the RxBUF Register.
After a byte of data has been received by the SPI Shift Register, a Receive
Character Available (RCA/IRQ3) flag and interrupt is generated. The next
byte of data will be received at this time. The RxBUF Register must be
cleared, or a Receive Character Overrun (RxCharOverrun) flag will be set
in the SCON Register, and the data in the RxBUF Register will be over-
written. When the communication between the master and slave is com-
plete, the SS goes inactive.When the SPI is activated as a slave, it operates
in all system modes: STOP, HALT, and RUN.
Unless disconnected, for every bit that is transferred into the slave
through the DI pin, a bit is transferred out through the D0 pin on the oppo-
site clock edge. During slave operation, the SPI clock pin (SK) is an
input. In master mode, the CPU must first activate a SS through one of its
I/O ports. Next, data is transferred through the master’s D0 pin one bit per
master clock cycle. Loading data into the shift register initiates the trans-
fer. In master mode, the master’s clock will drive the slave’s clock. At the
conclusion of a transfer, a Receive Character Available (RCA/IRQ3) flag
UM001602-0904
Serial Input/Output