Z86E3016PSG Datasheet, PDF (74/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
56
WDTMR (F) 0F
D7 D6 D5 D4 D3 D2 D1 D0
WDT
TAP*
00
01**
10
11
INT
RC
OSC
5
10
20
80
SYS
CLK
128
256
512
2048
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
XTAL1/INT RC
Select for WDT
0 On-Board RC *
1 XTAL
Reserved (Must be 0)
* Must be 0 for Z86C03
** Default setting after RESET
Figure 26. Example of Z8 Watch–Dog Timer Mode Register (Write-
Only)
The WDTMR register is accessible only during the first 60 processor
cycles from the execution of the first instruction after Power-On Reset,
Watch–Dog Reset or a Stop-Mode Recovery. After this point, the register
cannot be modified by any means, intentional or otherwise. The WDTMR
is a write-only register.
WDTMR is located in Expanded Register File Bank F, register 0Fh. This
register’s control bits are described on the next two pages.
Watch–Dog Timer
UM001602-0904