SAA7108AE Datasheet, PDF (96/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
10.6 Host port for 16-bit extension of video data I/O (H port)
The H port pins HPD can be used for extension of the data I/O paths to 16-bit.
The I port has functional priority. If I8_16[93h[6]] is set to logic 1 the output drivers of the
H port are enabled depending on the I port enable control. For I8_16 = 0, the HPD output
is disabled.
Table 47. Signals dedicated to the host port
Symbol Pin
I/O Description
Bit
HPD7 to A13, D12, I/O
HPD0 C12, B12,
A12, C11,
B11 and A11
16-bit extension for digital I/O (chrominance IPE[1:0] 87h[1:0],
component)
ITRI[8Fh[6]] and
I8_16[93h[6]]
10.7 Basic input and output timing diagrams for the I and X ports
10.7.1 I port output timing
Figure 43 to Figure 49 illustrate the output timing via the I port. IGPH and IGPV are logic 1
active gate signals. If reference pulses are programmed, these pulses are generated on
the rising edge of the logic 1 active gates. Valid data is accompanied by the output data
qualifier on pin IDQ. In addition, invalid cycles are marked with output code 00h.
The IDQ output pin may be defined to be a gated clock output signal
(ICLK AND internal IDQ).
10.7.2 X port input timing
At the X port the input timing requirements are the same as those for the I port output. But
different to those below:
• It is not necessary to mark invalid cycles with a 00h code
• No constraints on the input qualifier (can be a random pattern)
• XCLK may be a gated clock (XCLK AND external XDQ)
Remark: All timings illustrated in Figure 43 to Figure 49 are given for an uninterrupted
output stream (no handshake with the external hardware).
ICLK
IDQ
IPD[7:0] 00 FF 00
00 SAV 00 CB
Y
C_R
Y
00
IGPH
Fig 43. Output timing I port for serial 8-bit data at start of a line (ICODE = 1)
C_B
Y
C_R
Y
00
mhb550
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
96 of 208