SAA7108AE Datasheet, PDF (128/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 132. Input path control register, subaddress FDh, bit description
Bit Symbol Access Value Description
7
LUTOFF R/W
color look-up table
0
active
1
bypassed
6
CMODE R/W
cursor mode
0
cursor mode; input color will be inverted
1
auxiliary cursor color will be inserted
5
LUTL R/W
LUT loading via input data stream
0
inactive
1
color and cursor LUTs are loaded
4 to 2 IF[2:0] R/W
input format
000 8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB or C_B-Y-C_R
001 5 + 5 + 5-bit 4 : 4 : 4 non-interlaced RGB
010 5 + 6 + 5-bit 4 : 4 : 4 non-interlaced RGB
011 8 + 8 + 8-bit 4 : 2 : 2 non-interlaced C_B-Y-C_R
100 8 + 8 + 8-bit 4 : 2 : 2 interlaced C_B-Y-C_R (ITU-R BT.656,
27 MHz clock) (in subaddresses 91h and 94h set
XPIX = number of active pixels/line)
101 8-bit non-interlaced index color
110 8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB or C_B-Y-C_R (special
bit ordering)
1
MATOFF R/W
RGB to C_R-Y-C_B matrix
0
active
1
bypassed
0
DFOFF R/W
down formatter
0
(4 : 4 : 4 to 4 : 2 : 2) in input path is active
1
bypassed
Table 133. Cursor bit map register, subaddress FEh, bit description
Data byte Description
CURSA
RAM start address for cursor bit map; the byte following subaddress FEh points to
the first cell to be loaded with the next transmitted byte; succeeding cells are loaded
by auto-incrementing until stop condition
Table 134. Color look-up table register, subaddress FFh, bit description
Data byte Description
COLSA
RAM start address for color LUT; the byte following subaddress FFh points to the
first cell to be loaded with the next transmitted byte; succeeding cells are loaded by
auto-incrementing until stop condition
In subaddresses 5Bh, 5Ch, 5Dh, 5Eh, 62h and D3h all IRE values are rounded up.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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