SAA7108AE Datasheet, PDF (83/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
As a further option, it is possible to provide the scaler with an external gating signal on
pin ITRDY. Thereby making it possible to hold the data output for a certain time and to get
valid output data in bursts of a guaranteed length.
The sketched reference signals and events can be mapped to the I port output pins IDQ,
IGPH, IGPV, IGP0 and IGP1. For flexible use the polarities of all the outputs can be
modified. The default polarity for the qualifier and reference signals is logic 1 (active).
Table 32 shows the relevant and supported SAV and EAV coding.
Table 32. SAV/EAV codes on the I port
Event description
SAV/EAV codes on I port^[1] (hexadecimal)
MSB^[2] of SAV/EAV byte = 0
MSB^[2] of SAV/EAV byte = 1
Field ID = 0 Field ID = 1 Field ID = 0 Field ID = 1
Next pixel is FIRST pixel of any 0E
49
80
C7
active line
Previous pixel was LAST pixel of 13
54
9D
DA
any active line, but not the last
Next pixel is FIRST pixel of any 25
62
AB
EC
V-blanking line
Previous pixel was LAST pixel of 38
7F
B6
F1
the last active line or of any
V-blanking line
No valid data, do not capture 00
and do not increment pointer
Comment
HREF = active;
VREF = active
HREF = inactive;
VREF = active
HREF = active;
VREF = inactive
HREF = inactive;
VREF = inactive
IDQ pin inactive
[1] The leading byte sequence is: FFh-00h-00h.
[2] The MSB of the SAV/EAV code byte is controlled by:
a) Scaler output data: task A ⇒ MSB = CONLH[90h[7]]; task B ⇒ MSB = CONLH[C0h[7]].
b) VBI data slicer output data: DID[5:0] 5Dh[5:0] = 3Eh ⇒ MSB = 1; DID[5:0] 5Dh[5:0] = 3Fh ⇒ MSB = 0.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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