SAA7108AE Datasheet, PDF (105/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 49. Explanations of Figure 50 and Figure 51
Code
Description
S
START condition
Sr
repeated START condition
1000 100X^[1]
slave address
A
acknowledge generated by the slave
Am
acknowledge generated by the master
SUBADDRESS^[2]
subaddress byte
DATA
data byte
--------
continued data bytes and acknowledges
P
STOP condition
RAM ADDRESS
start address for RAM access
[1] X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read.
[2] If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed.
11.1.2 Slave receiver
Table 50. Common DAC adjust fine register, subaddress 16h, bit description
Legend: * = default value after reset.
Bit Symbol Access Value Description
7 to 4 -
R/W 0
must be programmed with logic 0 to ensure compatibility to
future enhancements
3 to 0 DACF[3:0] R/W
DAC fine output voltage adjustment, 1 % steps for all DACs
0111 7 %
0110 6 %
0101 5 %
0100 4 %
0011 3 %
0010 2 %
0001 1 %
0000* 0 %
1000 0 %
1001 −1 %
1010 −2 %
1011 −3 %
1100 −4 %
1101 −5 %
1110 −6 %
1111 −7 %
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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