SAA7108AE Datasheet, PDF (43/208 Pages) NXP Semiconductors – HD-CODEC

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CVBS-IN
or CHR-IN
CVBS-IN
or Y-IN
LDEL
YCOMB
DELAY
COMPENSATION
Y
SUBTRACTOR
CHR
QUADRATURE
MODULATOR
C_B-C_{R INTERPOLATION}
LOW-PASS 3
LUBW C_B-C_R
LUMINANCE-PEAKING
OR
LOW-PASS,
Y-DELAY ADJUSTMENT
LUFI[3:0] SET_RAW
CSTD[2:0] SET_VBI
YDEL [ 2:0]
Y/ CVBS
DBRI [ 7:0]
DCON [ 7:0]
DSAT [ 7:0]
RAWG [ 7:0]
RAWO [ 7:0]
COLO
QUADRATURE
DEMODULATOR
LOW-PASS 1
DOWNSAMPLING
ADAPTIVE
COMB FILTER
C_B-C_R LOW-PASS 2
SUBCARRIER
GENERATION 2
CHROMINANCE
INCREMENT
DELAY
SUBCARRIER
GENERATION 1
HUEC[7:0]
LCBW[2:0]
LDEL
YCOMB
SET_RAW
SET_VBI
CCOMB
YCOMB
LDEL
BYPS
CHROMINANCE
INCREMENT
DTO RESET
SUBCARRIER
INCREMENT
GENERATION
AND
DIVIDER
PHASE
DEMODULATOR
AMPLITUDE
DETECTOR
BURST GATE
ACCUMULATOR
LOOP FILTER
CHBW
SECAM
PROCESSING
CHROMA
GAIN
CONTROL
C_B-C_R
ADJUSTMENT
BRIGHTNESS
CONTRAST
SATURATION
CONTROL
RAW DATA
GAIN AND
OFFSET
CONTROL
Y-OUT/
CVBS-OUT
C_B-C_R-OUT
HREF-OUT
C_B-C_R SET_RAW
SET_VBI
PAL DELAY LINE
SECAM
RECOMBINATION
CDTO
CSTD [ 2:0]
RTCO
FCTC
ACGC
CGAIN [ 6:0]
IDEL [ 3:0]
CODE
BRIG[7:0]
CONT[7:0]
SATN[7:0]
SET_RAW
SET_VBI
f_H/2 switch signal
DCVF
mhb532
Fig 19. Chrominance and luminance processing