SAA7108AE Datasheet, PDF (139/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 144. Analog input control 1 (AICO1); 02h[7:0] …continued
Bit
Description
Symbol Value Function
3 to 0
mode selection
MODE[3:0] 0000 Mode 0: CVBS (automatic gain) from AI11
(pin P13); see Figure 53
0001 Mode 1: CVBS (automatic gain) from AI12
(pin P11); see Figure 54
0010 Mode 2: CVBS (automatic gain) from AI21
(pin P10); see Figure 55
0011 Mode 3: CVBS (automatic gain) from AI22
(pin P9); see Figure 56
0100 Mode 4: CVBS (automatic gain) from AI23
(pin P7); see Figure 57
0101 Mode 5: CVBS (automatic gain) from AI24
(pin P6); see Figure 58
0110
Mode 6: Y (automatic gain) from AI11
(pin P13) + C (gain adjustable via
GAI28 to GAI20) from AI21 (pin P10)^[1];
see Figure 59
0111
Mode 7: Y (automatic gain) from AI12
(pin P11) + C (gain adjustable via
GAI28 to GAI20) from AI22 (pin P9)^[1];
see Figure 60
1000 Mode 8: Y (automatic gain) from AI11
(pin P13) + C (gain adapted to Y gain) from
AI21 (pin P10)^[1]; see Figure 61
1001 Mode 9: Y (automatic gain) from AI12
(pin P11) + C (gain adapted to Y gain) from
AI22 (pin P9)^[1]; see Figure 62
1010 Modes 10 to 15: reserved
to
1111
[1] To take full advantage of the Y/C modes 6 to 9, the I²C-bus bit BYPS (subaddress 09h, bit 7) should be set
to logic 1 (full luminance bandwidth).
AI24
AI23
AD2
AI22
AI21
AI24
CHROMA
AI23
AI22
AD2
AI21
CHROMA
AI12
AD1
AI11
LUMA
mhb559
AI12
AI11
AD1
LUMA
mhb560
Fig 53. Mode 0 CVBS (automatic gain)
Fig 54. Mode 1 CVBS (automatic gain)
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
139 of 208