SAA7108AE Datasheet, PDF (38/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
9. Functional description of digital video decoder part
9.1 Decoder
9.1.1 Analog input processing
The SAA7108AE; SAA7109AE offers six analog signal inputs, two analog main channels
with source switch, clamp circuit, analog amplifier, anti-alias filter and video 9-bit CMOS
ADC; see Figure 16.
9.1.2 Analog control circuits
The anti-alias filters are adapted to the line-locked clock frequency via a filter control
circuit. The characteristic is shown in Figure 13. During the vertical blanking period gain
and clamping control are frozen.
6
V
(dB)
0
−6
mgd138
−12
−18
−24
−30
−36
−42
0
2
4
6
8
10
12
14
f (MHz)
Fig 13. Anti-alias filter
9.1.2.1 Clamping
The clamp control circuit controls the correct clamping of the analog input signals.
The coupling capacitor is also used to store and filter the clamping voltage. An internal
digital clamp comparator generates the information with respect to clamp-up or
clamp-down. The clamping levels for the two ADC channels are fixed for luminance (60)
and chrominance (128). Clamping time in normal use is set with the HCL pulse on the
back porch of the video signal; see Figure 14 and Figure 15.
9.1.2.2
Gain control
The gain control circuit receives (via the I²C-bus) the static gain levels for the two analog
amplifiers or controls one of these amplifiers automatically via a built-in Automatic Gain
Control (AGC) as part of the Analog Input Control (AICO).
The AGC for luminance is used to amplify a CVBS or Y signal to the required signal
amplitude, matched to the ADCs input voltage range. The AGC active time is the sync
bottom of the video signal.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
38 of 208