SAA7108AE Datasheet, PDF (169/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
11.2.5.9 Subaddresses A0h to A2h
Table 216. Horizontal prescaling; register set A [A0h[5:0]] and B [D0h[5:0]]
Horizontal integer prescaling Control bits 5 to 0
ratio (XPSC)
XPSC5 XPSC4 XPSC3 XPSC2 XPSC1
Not allowed
0
0
0
0
0
Downscale = 1
0
0
0
0
0
Downscale = ¹â„₂
...
0
0
0
0
1
...
...
...
...
...
Downscale = ¹â„₆₃
1
1
1
1
1
XPSC0
0
1
0
...
1
Table 217. Accumulation length; register set A [A1h[5:0]] and B [D1h[5:0]]
Horizontal prescaler accumulation Control bits 5 to 0
sequence length (XACL)
XACL5 XACL4 XACL3 XACL2 XACL1 XACL0
Accumulation length = 1
0
0
0
0
0
0
Accumulation length = 2
0
0
0
0
0
1
...
...
...
...
...
...
...
Accumulation length = 64
1
1
1
1
1
1
Table 218. Prescaler DC gain and FIR prefilter control; register set A [A2h[7:4]] and
B [D2h[7:4]]^[1]
FIR prefilter control
Control bits 7 to 4
PFUV1 PFUV0 PFY1
PFY0
Luminance FIR filter bypassed
X
X
0
0
H_y(z) = ¹â„₄ (1 2 1)
H_y(z) = ¹â„₈ (−1 1 1.75 4.5 1.75 1 −1)
H_y(z) = ¹â„₈ (1 2 2 2 1)
Chrominance FIR filter bypassed
X
X
0
1
X
X
1
0
X
X
1
1
0
0
X
X
H_uv(z) = ¹â„₄ (1 2 1)
H_uv(z) = ¹â„₃₂ (3 8 10 8 3)
H_uv(z) = ¹â„₈ (1 2 2 2 1)
0
1
X
X
1
0
X
X
1
1
X
X
[1] X = don’t care.
SAA7108AE_SAA7109AE_3
Product data sheet
Table 219. Prescaler DC gain and FIR prefilter control; register set A [A2h[3:0]] and
B [D2h[3:0]]^[1]
Prescaler DC gain
Control bits 3 to 0
XC2_1 XDCG2 XDCG1 XDCG0
Prescaler output is renormalized by gain factor = 1 X
0
0
0
Prescaler output is renormalized by gain factor = ¹â„₂ X
0
0
1
Prescaler output is renormalized by gain factor = ¹â„₄ X
0
1
0
Prescaler output is renormalized by gain factor = ¹â„₈ X
0
1
1
Prescaler output is renormalized by gain factor = ¹â„₁₆ X
1
0
0
Prescaler output is renormalized by gain factor = ¹â„₃₂ X
1
0
1
Prescaler output is renormalized by gain factor = ¹â„₆₄ X
1
1
0
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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