SAA7108AE Datasheet, PDF (198/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
18. Test information
18.1 Boundary scan test
The SAA7108AE; SAA7109AE has built-in logic and 2 times 5 dedicated pins to support
boundary scan testing, separately for the encoder and decoder part, which allows board
testing without special hardware (nails). The SAA7108AE; SAA7109AE follows the “IEEE
Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture” set by the Joint
Test Action Group (JTAG) chaired by NXP.
The 10 special pins are Test Mode Select (TMSe and TMSd), Test Clock
(TCKe and TCKd), Test Reset (TRSTe and TRSTd), Test Data Input (TDIe and TDId) and
Test Data Output (TDOe and TDOd), where extension ‘e’ refers to the encoder part and
extension ‘d’ refers to the decoder part.
The Boundary Scan Test (BST) functions BYPASS, EXTEST, SAMPLE, CLAMP and
IDCODE are all supported; see Table 242. Details about the JTAG BST-TEST can be
found in the specification “IEEE Std. 1149.1”. Two files containing the detailed Boundary
Scan Description Language (BSDL) of the SAA7108AE; SAA7109AE are available on
request.
Table 242. BST instructions supported by the SAA7108AE; SAA7109AE
Instruction Description
BYPASS
This mandatory instruction provides a minimum length serial path (1 bit) between
TDIe (or TDId) and TDOe (or TDOd) when no test operation of the component is
required.
EXTEST
This mandatory instruction allows testing of off-chip circuitry and board level
interconnections.
SAMPLE
This mandatory instruction can be used to take a sample of the inputs during
normal operation of the component. It can also be used to preload data values into
the latched outputs of the boundary scan register.
CLAMP
This optional instruction is useful for testing when not all ICs have BST. This
instruction addresses the bypass register while the boundary scan register is in
external test mode.
IDCODE
This optional instruction will provide information on the components manufacturer,
part number and version number.
18.1.1 Initialization of boundary scan circuit
The Test Access Port (TAP) controller of an IC should be in the reset state
(TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces
the instruction register into a functional instruction such as IDCODE or BYPASS.
To solve the power-up reset, the standard specifies that the TAP controller will be forced
asynchronously to the TEST_LOGIC_RESET state by setting the TRSTe or TRSTd pin
LOW.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
198 of 208