SAA7108AE Datasheet, PDF (33/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
TPclk = -------------------²---⁶---²---^.-⁵-----^×-----¹---⁷---¹---⁶----^×-----^T----^X----^c---^l--^k------------------- (60 Hz)
InPpl × integer_-^I--^nO---^L--_u--ⁱ-_t-ⁿ-_L---⁺-_i--_n--²-- × 262.5_
TPclk = -------------------³---¹---²---^.-⁵-----^×-----¹---⁷---²---⁸----^×-----^T----^X----^c---^l--^k------------------- (50 Hz) and for the pixel clock generator
InPpl × integer_-^I--^nO---^L--_u--ⁱ-_t-ⁿ-_L---⁺-_i--_n--²-- × 312.5_
PCL = ^TT----^XP----^cc---^ll--^kk- × 2^{20 + PCLE} (all frequencies); see Table 88 and Table 89. The divider PCLE
should be set according to Table 89. PCLI may be set to a lower or the same value.
Setting a lower value means that the internal pixel clock is higher and the data get
sampled up. The difference may be 1 at 640 × 480 pixels resolution and 2 at resolutions
with 320 pixels per line as a rule of thumb. This allows horizontal upscaling by a maximum
factor of 2 respectively 4 (this is the parameter RiePclk).
PCLI = PCLE – ^l--^o---^g----^R-_l-_o--ⁱ-_g-^e---_2P----^c---^l--^k- (all frequencies)
The equations ensure that the last line of the field has the full number of clock cycles.
Many graphic controllers require this. Note that the bit PCLSY needs to be set to ensure
that there is not even a fraction of a clock left at the end of the field.
8.20.3 Horizontal scaler
XOFS can be chosen arbitrarily, the condition being that XOFS + XPIX ≤ HLEN is fulfilled.
Values given by the VESA display timings are preferred.
HLEN = InPpl × RiePclk − 1
XPIX = -^I--ⁿ---_2P----ⁱ--^x- × RiePclk
XINC = ^O---_I--_nu---_P-^t--^P-_i---_xi--^x- × -_R----_i4--_e-⁰--_P-⁹---_c6---_l--_k-
XINC needs to be rounded up, it needs to be set to 0 for a scaling factor of 1.
8.20.4 Vertical scaler
The input vertical offset can be taken from the assumption that the scaler should just have
finished writing the first line when the encoder starts reading it:
YOFS = ^F-----^A---_I-^L-_n---^×-_P----_p1---_l7---¹_×---⁶--_T---^×-_P---^T-_c---_lX--_k--^c---^l--^k- – 2.5 (60 Hz) YOFS = ^F-----^A---_I-^L-_n---^×-_P----_p1---_l7---²_×---⁸--_T---^×-_P---^T-_c---_lX--_k--^c---^l--^k- – 2.5 (50 Hz)
In most cases the vertical offsets will be the same for odd and even fields. The results
should be rounded down.
YPIX = InLin
YSKIP defines the anti-flicker function. 0 means maximum flicker reduction but minimum
vertical bandwidth, 4095 gives no flicker reduction and maximum bandwidth. Note that the
maximum value for YINC is 4095. It might be necessary to reduce the value of YSKIP to
fulfil this requirement.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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