SAA7108AE Datasheet, PDF (158/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 186. Global control 1; global set 80h[3:0]^[1]
I port and scaler back-end clock selection
ICLK output and back-end clock is line-locked clock LLC from
decoder
ICLK output and back-end clock is XCLK from X port
ICLK output is LLC and back-end clock is LLC2 clock
Back-end clock is the ICLK input
IDQ pin carries the data qualifier
IDQ pin carries a gated back-end clock (IDQ AND CLK)
IDQ generation only for valid data
IDQ qualifies valid data inside the scaling region and all data
outside the scaling region
Control bits 3 to 0
ICKS3 ICKS2 ICKS1 ICKS0
X
X
0
0
X
X
0
1
X
X^[2]
1
0
X
X
1
1
X
0
X
X
X
1
X
X
0
X
X
X
1
X
X
X
[1] X = don’t care.
[2] Although the ICLK I/O is independent of ICKS2 and ICKS3, this selection can only be used if ICKS2 = 1.
11.2.5.2 Subaddresses 83h to 87h
Table 187. X port I/O enable and output clock phase control; global set 83h[5:4]
Output clock phase control
Control bits 5 and 4
XPCK1
XPCK0
XCLK default output phase, recommended value
0
0
XCLK output inverted
0
1
XCLK phase shifted by approximately 3 ns
1
0
XCLK output inverted and shifted by approximately 3 ns
1
1
Table 188. X port I/O enable and output clock phase control; global set 83h[2:0]^[1]
X port I/O enable
Control bits 2 to 0
XRQT XPE1 XPE0
X port output is disabled by software
X
0
0
X port output is enabled by software
X
0
1
X port output is enabled by pin XTRI at logic 0
X
1
0
X port output is enabled by pin XTRI at logic 1
X
1
1
XRDY output signal is A/B task flag from event handler (A = 1) 0
X
X
XRDY output signal is ready signal from scaler path (XRDY = 1 1
X
X
means the SAA7108AE; SAA7109AE is ready to receive data)
[1] X = don’t care.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
158 of 208