SAA7108AE Datasheet, PDF (156/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
11.2.4.3 Subaddress 58h
Table 177. Programmable framing code; slicer set 58h[7:0]; see Table 28 and Table 176
Framing code for programmable data types
Control bits 7 to 0
Default value
FC[7:0] = 40h
11.2.4.4 Subaddress 59h
Table 178. Horizontal offset for slicer; slicer set 59h and 5Bh
Horizontal offset
Control bits 5Bh[2:0]
Control bits 59h[7:0]
Recommended value
HOFF[10:8] = 3h
HOFF[7:0] = 47h
11.2.4.5 Subaddress 5Ah
Table 179. Vertical offset for slicer; slicer set 5Ah and 5Bh
Vertical offset
Control bit 5Bh[4]
VOFF8
Minimum value 0
0
Maximum value 312
1
Value for 50 Hz 625 lines input 0
Value for 60 Hz 525 lines input 0
Control bits 5Ah[7:0]
VOFF[7:0]
00h
38h
03h
06h
11.2.4.6 Subaddress 5Bh
Table 180. Field offset, and MSBs for horizontal and vertical offsets; slicer set 5Bh[7:6]
See Section 11.2.4.4 and Section 11.2.4.5 for HOFF[10:8] 5Bh[2:0] and VOFF8[5Bh[4]].
Bit Description Symbol Value Function
7 field offset
FOFF
0
no modification of internal field indicator (default for
50 Hz 625 lines input sources)
1
invert field indicator (default for 60 Hz 525 lines input
sources)
6 recode
RECODE 0
leave data unchanged (default)
1
convert 00h and FFh data bytes into 03h and FCh
11.2.4.7 Subaddress 5Dh
Table 181. Header and data identification (DID; ITU 656) code control; slicer set 5Dh[7:0]
Bit
Description
Symbol Value
Function
7
field ID and V-blank
FVREF 0
selection for text output
(F and V reference
1
selection)
F and V output of slicer is LCR table
dependent
F and V output is taken from decoder
real-time signals EVEN_ITU and
VBLNK_ITU
5 to 0 default; DID[5:0] = 00h DID[5:0] 00 0000
ANC header framing; see Figure 42
and Table 34
special cases of DID
programming
11 1110
DID[5:0] = 3Eh SAV/EAV framing, with
FVREF = 1
11 1111
DID[5:0] = 3Fh SAV/EAV framing, with
FVREF = 0
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
156 of 208