SAA7108AE Datasheet, PDF (111/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 63. VPS enable, input control 2, subaddress 54h, bit description …continued
Legend: * = default value after reset.
Bit
Symbol Access Value Description
1
EDGE R/W
input data is sampled with
0
inverse clock edges
1* the clock edges specified in Table 12 to Table 18
0
SLOT R/W 0* normal assignment of the input data to the clock edge
1
correct time misalignment due to inverted assignment of input
data to the clock edge
Table 64. VPS byte 5, 11, 12, 13 and 14 registers, subaddresses 55h to 59h, bit
description^[1]
Subaddress Bit Symbol Access Value Description
55h
7 to 0 VPS5[7:0] R/W -
fifth byte of video programming system data
56h
7 to 0 VPS11[7:0] R/W -
eleventh byte of video programming system
data
57h
7 to 0 VPS12[7:0] R/W -
twelfth byte of video programming system
data
58h
7 to 0 VPS13[7:0] R/W -
thirteenth byte of video programming system
data
59h
7 to 0 VPS14[7:0] R/W -
fourteenth byte of video programming system
data
[1] In line 16; LSB first; all other bytes are not relevant for VPS.
Table 65. Chrominance phase register, subaddress 5Ah, bit description
Legend: * = default value after reset.
Bit
Symbol Access Value Description
7 to 0 CHPS[7:0] R/W
00h* phase of encoded color subcarrier (including burst) relative
to horizontal sync; can be adjusted in steps of
360/256 degrees
6Bh PAL B/G and data from input ports in Master mode
16h PAL B/G and data from look-up table
25h NTSC M and data from input ports in Master mode
46h NTSC M and data from look-up table
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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