SAA7108AE Datasheet, PDF (143/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 150. Sync control; 08h[7:0] …continued
Bit
Description
Symbol Value
4 and 3 horizontal time
HTC[1:0] 00
constant selection
01
2
horizontal PLL
1 and 0 vertical noise
reduction
10
11
HPLL
0
1
VNOI[1:0] 00
01
10
11
Function
TV mode, recommended for poor quality TV
signals only; do not use for new applications
VTR mode, recommended if a deflection
control circuit is directly connected to the
SAA7108AE; SAA7109AE
reserved
fast locking mode; recommended setting
PLL closed
PLL open; horizontal frequency fixed
normal mode; recommended setting
fast mode, applicable for stable sources only;
automatic field detection (AUFD) must be
disabled
free running mode
vertical noise reduction bypassed
11.2.2.10 Subaddress 09h
Table 151. Luminance control; 09h[7:0]
Bit
Description
Symbol Value
7
chrominance
BYPS 0
trap/comb filter
bypass
1
6
adaptive luminance YCOMB 0
comb filter
1
5
processing delay in LDEL
0
non comb filter
mode
1
4
remodulation
LUBW 0
bandwidth for
luminance; see
Figure 22 to
1
Figure 25
Function
chrominance trap or luminance comb filter
active; default for CVBS mode
chrominance trap or luminance comb filter
bypassed; default for S-video mode
disabled (= chrominance trap enabled, if
BYPS = 0)
active, if BYPS = 0
processing delay is equal to internal
pipe-lining delay
one (NTSC standards) or two (PAL
standards) video lines additional processing
delay
small remodulation bandwidth (narrow
chrominance notch ⇒ higher luminance
bandwidth)
large remodulation bandwidth (wider
chrominance notch ⇒ smaller luminance
bandwidth)
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
143 of 208