SAA7108AE Datasheet, PDF (121/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 97. Scaler CTRL, MCB and YPIX register, subaddress 96h, bit description
Bit
Symbol Access Value Description
7
EFS
R/W
in Slave mode frame sync signal at pin FSVGC
0
ignored
1
accepted
6
PCBN R/W
polarity of CBO signal
0
normal (HIGH during active video)
1
inverted (LOW during active video)
5
SLAVE R/W
from the SAA7104E; SAA7105E the timing to the graphics
controller is
0
master
1
slave
4
ILC
R/W
if hardware cursor insertion is active
0
set LOW for non-interlaced input signals
1
set HIGH for interlaced input signals
3
YFIL
R/W
luminance sharpness booster
0
disabled
1
enabled
2
-
R/W 0
must be programmed with logic 0 to ensure compatibility to
future enhancements
1 and 0 YPIX[9:8]
see Table 96
Table 98. Sync control register, subaddress 97h, bit description
Bit
Symbol Access Value Description
7
HFS
R/W
horizontal sync is derived from
0
input signal (Save mode) at pin HSVGC
1
a frame sync signal (Slave mode) at pin FSVGC (only if EFS
is set HIGH)
6
VFS
R/W
vertical sync (field sync) is derived from
0
input signal (Slave mode) at pin VSVGC
1
a frame sync signal (Slave mode) at pin FSVGC (only if EFS
is set HIGH)
5
OFS
R/W
pin FSVGC is
0
input
1
active output
4
PFS
R/W
polarity of signal at pin FSVGC in output mode (Master
mode) is
0
active HIGH; rising edge of the input signal is used in Slave
mode
1
active LOW; falling edge of the input signal is used in Slave
mode
3
OVS
R/W
pin VSVGC is
0
input
1
active output
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
121 of 208