SAA7108AE Datasheet, PDF (123/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 103. MSBs vertical and horizontal increment register, subaddress 9Ch, bit description
Bit
Symbol
Description
7 to 4
YINC[11:8] see Table 102
3 to 0
XINC[11:8] see Table 101
Table 104. Weighting factor odd register, subaddress 9Dh, bit description
Bit
Symbol
Description
7 to 0
YIWGTO[7:0] with YIWGTO[11:8] (see Table 106) weighting factor for the first line
of the odd field; YIWGTO = ^{Y----I--N----C--} + 2048
2
Table 105. Weighting factor even, subaddress 9Eh, bit description
Bit
Symbol
Description
7 to 0
YIWGTE[7:0] with YIWGTE[11:8] (see Table 106) weighting factor for the first line
of the even field; YIWGTE = ^{Y----I--N----C-----–}-----Y---S---K----I--P--
2
Table 106. Weighting factor MSB register, subaddress 9Fh, bit description
Bit
Symbol
Description
7 to 4
YIWGTE[11:8] see Table 105
3 to 0
YIWGTO[11:8] see Table 104
Table 107. Vertical line skip register, subaddress A0h, bit description
Bit
Symbol
Access Value Description
7 to 0
YSKIP[7:0] R/W
with YSKIP[11:8] (see Table 108) vertical line skip;
defines the effectiveness of the anti-flicker filter
000h most effective
FFFh anti-flicker filter switched off
Table 108. Blank enable for NI-bypass, vertical line skip MSB register, subaddress A1h, bit
description
Legend: * = default value after reset.
Bit
Symbol
Access Value Description
7
BLEN
R/W
for non-interlaced graphics in bypass mode
0* no internal blanking
1
forced internal blanking
6 to 4
-
R/W 000 must be programmed with logic 0 to ensure
compatibility to future enhancements
3 to 0
YSKIP[11:8] R/W
see Table 107
Table 109. Border color Y register, subaddress A2h, bit description
Bit
Symbol
Description
7 to 0
BCY[7:0]
luminance portion of border color in underscan area
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
123 of 208