SAA7108AE Datasheet, PDF(178/208 Page) NXP Semiconductors

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SAA7108AE Datasheet, PDF (178/208 Pages) NXP Semiconductors – HD-CODEC

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NXP Semiconductors

SAA7108AE; SAA7109AE

HD-CODEC

SAA7108AE_SAA7109AE_3

Product data sheet

Table 236. Scaler and interface conï¬guration example

I2C-bus Main functionality

address

(hex)

Example 1 Example 2

Hex Dec Hex Dec

Global settings

task enable, IDQ and back-end 10 -

10 -

clock deï¬nition

XCLK output phase and X port 01 -

01 -

output enable

IGPH, IGPV, IGP0 and IGP1 A0 -

C5 -

output deï¬nition

signal polarity control and I port 10 -

09 -

byte swapping

FIFO ï¬ag thresholds and

45 -

40 -

video/text arbitration

ICLK and IDQ output phase 01 -

01 -

and I port enable

power save control and

software reset

F0 -

Task A: scaler input conï¬guration and output format settings

task handling

00 -

scaler input source and format 08 -

08 -

deï¬nition

reference signal deï¬nition at 10 -

10 -

scaler input

I port output formats and

80 -

40 -

conï¬guration

Input and output window deï¬nition

horizontal input offset (XO)

10 16 10 16

00 -

horizontal input (source)

window length (XS)

D0 720 C0 704

02 -

vertical input offset (YO)

0A 10 0A 10

00 -

vertical input (source) window F2 242 22 290

length (YS)

00 -

01 -

horizontal output (destination) D0 720 00 768

window length (XD)

02 -

03 -

vertical output (destination)

F0 240 20 288

window length (YD)

00 -

01 -

Preï¬ltering and prescaling

integer prescale (value â00â not 01 -

01 -

allowed)

accumulation length for

prescaler

00 -

FIR preï¬lter and prescaler DC 00 -

00 -

normalization

Example 3

Hex Dec

10 -

00 -

A0 -

10 -

45 -

01 -

F0 -

00 -

18 -

10 -

80 -

10 16

00 -

D0 720

02 -

0A 10

00 -

F2 242

00 -

60 352

01 -

20 288

01 -

02 -

AA -

Example 4

Hex Dec

10 -

00 -

A0 -

10 -

45 -

01 -

F0 -

00 -

38 -

10 -

84 -

10 16

00 -

D0 720

02 -

0A 10

00 -

22 290

01 -

C8 200

00 -

50 80

00 -

02 -

03 -

F2 -

Rev. 03 â 6 February 2007

178 of 208

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