SAA7108AE Datasheet, PDF (93/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 44. 525 lines/60 Hz vertical timing
Line
number
F (ITU 656)
V
OFTS[2:0] = 000 (ITU 656)
1 to 3
1
1
4 to 19
0
1
20
0
0
21
0
0
22 to 261 0
0
262
0
0
263
0
0
264 and 265 0
1
266 to 282 1
1
283
1
0
284
1
0
285 to 524 1
0
525
1
0
OFTS[2:0] = 001
according to selected VGATE
position type via VSTA and VSTO
(subaddresses 15h to 17h);
see Table 164 to Table 166
Table 45. 625 lines/50 Hz vertical timing
Line
number
F (ITU 656)
V
OFTS[2:0] = 000 (ITU 656)
1 to 22
0
1
23
0
0
24 to 309 0
0
310
0
0
311 and 312 0
1
313 to 335 1
1
336
1
0
337 to 622 1
0
623
1
0
624 and 625 1
1
OFTS[1:0] = 10
according to selected VGATE
position type via VSTA and VSTO
(subaddresses 15h to 17h);
see Table 164 to Table 166
10.4.2 X port configured as input
If the data input mode is selected at the expansion port, then the scaler can select its input
data stream from the on-chip video decoder, or from the expansion port (controlled by bit
SCSRC[1:0] 91h[5:4]). Byte serial Y-C_B-C_R 4 : 2 : 2, or subsets for other sampling
schemes, or raw samples from an external ADC may be input (see also bits FSC[2:0]
91h[2:0]). The input data stream must be accompanied by an external clock (XCLK),
qualifier XDQ and reference signals XRH and XRV. Instead of the reference signal,
embedded SAV and EAV codes according to ITU 656 are also accepted. The protection
bits are not evaluated.
XRH and XRV carry the horizontal and vertical synchronization signals for the digital
video stream through the expansion port. The field ID of the input video stream is carried
in the phase (edge) of XRV and state of XRH, or directly as FS (frame sync, odd/even
signal) on the XRV pin (controlled by XFDV[92h[7]], XFDH[92h[6]] and XDV[1:0] 92h[5:4]).
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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