SAA7108AE Datasheet, PDF (21/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
8.2 Input formatter
The input formatter converts all accepted PD input data formats, either RGB or Y-C_B-C_R,
to a common internal RGB or Y-C_B-C_R data stream.
When double-edge clocking is used, the data is internally split into portions PPD1 and
PPD2. The clock edge assignment must be set according to the I²C-bus control bits SLOT
and EDGE for correct operation.
If Y-C_B-C_R is being applied as a 27 MB/s data stream, the output of the input formatter can
be used directly to feed the video encoder block.
The horizontal upscaling is supported via the input formatter. According to the
programming of the pixel clock dividers (see Section 8.10), it will sample up the data
stream to 1 ×, 2 × or 4 × the input data rate. An optional interpolation filter is available. The
clock domain transition is handled by a 4 entries wide FIFO which gets initialized every
field or explicitly at request. A bypass for the FIFO is available, especially for high input
data rates.
8.3 RGB LUT
The three 256-byte RAMs of this block can be addressed by three 8-bit wide signals, thus
it can be used to build any transformation, e.g. a gamma correction for RGB signals. In the
event that the indexed color data is applied, the RAMs are addressed in parallel.
The LUTs can either be loaded by an I²C-bus write access or can be part of the pixel data
input through the PD port. In the latter case, 256 bytes × 3 bytes for the R, G and B LUT
are expected at the beginning of the input video line, two lines before the line that has
been defined as first active line, until the middle of the line immediately preceding the first
active line. The first 3 bytes represent the first RGB LUT data, and so on.
8.4 Cursor insertion
A 32 dots × 32 dots cursor can be overlaid as an option; the bit map of the cursor can be
uploaded by an I²C-bus write access to specific registers or in the pixel data input through
the PD port. In the latter case, the 256 bytes defining the cursor bit map (2 bits per pixel)
are expected immediately following the last RGB LUT data in the line preceding the first
active line.
The cursor bit map is set up as follows: each pixel occupies 2 bits. The meaning of these
bits depends on the CMODE I²C-bus register as described in Table 8. Transparent means
that the input pixels are passed through, the ‘cursor colors’ can be programmed in
separate registers.
The bit map is stored with 4 pixels per byte, aligned to the least significant bit. So the first
pixel is in bits 0 and 1, the next pixel in bits 3 and 4 and so on. The first index is the
column, followed by the row; index 0,0 is the upper left corner.
Table 6. Layout of a byte in the cursor bit map
D7
D6
D5
D4
D3
pixel n + 3
pixel n + 2
D1
D0
D1
D0
D1
D2
pixel n + 1
D0
D1
D0
pixel n
D1
D0
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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