SAA7108AE Datasheet, PDF (24/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
8.10 Oscillator and Discrete Time Oscillator (DTO)
The master clock generation is realized as a 27 MHz crystal oscillator, which can operate
with either a fundamental wave crystal or a 3rd harmonic crystal.
The crystal clock supplies the DTO of the pixel clock synthesizer, the video encoder and
the I²C-bus control block. It also usually supplies the triple DAC, with the exception of the
auxiliary VGA mode, where the triple DAC is clocked by the pixel clock (PIXCLK).
The DTO can be programmed to synthesize all relevant pixel clock frequencies between
circa 40 MHz and 85 MHz. Two programmable dividers provide the actual clock to be
used externally and internally. The dividers can be programmed to factors of 1, 2, 4 and 8.
For the internal pixel clock, a divider ratio of 8 makes no sense and is thus forbidden.
The internal clock can be switched completely to the pixel clock input. In this event, the
input FIFO is useless and will be bypassed.
The entire pixel clock generation can be locked to the vertical frequency. Both pixel clock
dividers get re-initialized every field. Optionally, the DTO can be cleared with each V-sync.
At proper programming, this will make the pixel clock frequency a precise multiple of the
vertical and horizontal frequencies. This is required for some graphic controllers.
8.11 Low-pass Clock Generation Circuit (CGC)
This block reduces the phase jitter of the synthesized pixel clock. It works as a tracking
filter for all relevant synthesized pixel clock frequencies.
8.12 Encoder
8.12.1 Video path
The encoder generates luminance and color subcarrier output signals from the
Y, C_B and C_R baseband signals, which are suitable for use as CVBS or separate Y and C
signals.
Input to the encoder, at 27 MHz clock (e.g. DVD), is either originated from computer
graphics at pixel clock, fed through the FIFO and border generator, or a ITU-R BT.656
style signal.
Luminance is modified in gain and in offset (the offset is programmable in a certain range
to enable different black level set-ups). A blanking level can be set after insertion of a fixed
synchronization pulse tip level, in accordance with standard composite synchronization
schemes. Other manipulations used for the Macrovision anti-taping process, such as
additional insertion of AGC super-white pulses (programmable in height), are supported
by the SAA7108AE only.
To enable easy analog post filtering, luminance is interpolated from a 13.5 MHz data rate
to a 27 MHz data rate, thereby providing luminance in a 10-bit resolution. The transfer
characteristics of the luminance interpolation filter are illustrated in Figure 8 and Figure 9.
Appropriate transients at start/end of active video and for synchronization pulses are
ensured.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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