SAA7108AE Datasheet, PDF (34/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
YINC
=
-_I--_nO---_L--^u--_i-^t-_n-^L---₊-ⁱ--ⁿ--₂--
×


1
+
Y_---4-S_--0--K_-9---I5_--P_{--}
×
4096
YIWGTO = ^Y----^I--₂-^N----^C-- + 2048
YIWGTE = ^Y----^I---^N----^C------^–-₂---^Y----^S---^K-----^I--^P--
When YINC = 0 it sets the scaler to scaling factor 1. The initial weighting factors must not
be set to 0 in this case. YIWGTE may go negative. In this event, YINC should be added
and YOFSE incremented. This can be repeated as often as necessary to make YIWGTE
positive.
It should be noted that these equations assume that the input is non-interlaced but the
output is interlaced. If the input is interlaced, the initial weighting factors need to be
adapted to obtain the proper phase offsets in the output frame.
If vertical upscaling beyond the upper capabilities is required, the parameter YUPSC may
be set to logic 1. This extends the maximum vertical scaling factor by a factor of 2. Only
the parameter YINC is affected, it needs to be divided by two to get the same effect.
There are restrictions in this mode:
• The vertical filter YFIL is not available in this mode; the circuit will ignore this value
• The horizontal blanking needs to be long enough to transfer an output line between
2 memory locations. This is 710 internal pixel clocks
Or the upscaling factor needs to be limited to 1.5 and the horizontal upscaling factor is
also limited to less than ∼1.5. In this case a normal blanking length is sufficient
8.21 Input levels and formats
The SAA7108AE; SAA7109AE accepts digital Y, C_B, C_R or RGB data with levels (digital
codes) in accordance with ‘ITU-R BT.601’. An optional gain adjustment also allows to
accept data with the full level swing of 0 to 255.
For C and CVBS outputs, deviating amplitudes of the color difference signals can be
compensated for by independent gain control setting, while gain for luminance is set to
predefined values, distinguishable for 7.5 IRE set-up or without set-up.
The RGB, respectively C_R-Y-C_B path features an individual gain setting for luminance
(GY) and color difference signals (GCD). Reference levels are measured with a color bar,
100 % white, 100 % amplitude and 100 % saturation.
The encoder section of the SAA7108AE; SAA7109AE has special input cells for the VGC
port. They operate at a wider supply voltage range and have a strict input threshold at
1_{⁄2VDD(DVO). To achieve full speed of these cells, the EIDIV bit needs to be set to logic 1.}
Note that the impedance of these cells is approximately 6 kΩ. This may cause trouble with
the bootstrapping pins of some graphic chips. So the power-on reset forces the bit to
logic 0, the input impedance is regular in this mode.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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