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SAA7108AE Datasheet, PDF (184/208 Pages) NXP Semiconductors – HD-CODEC
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NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 240. Characteristics of the digital video decoder part
VDDD = 3.0 V to 3.6 V; VDDA = 3.1 V to 3.5 V; Tamb = 0 °C to 70 °C (typical values measured at Tamb = 25 °C); timings and
levels refer to drawings and conditions illustrated in Figure 67; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDDD
IDDD
PD
digital supply voltage
digital supply current
power dissipation digital
part
X port 3-state; 8-bit I port
3.15
3.3
-
90
-
300
3.45
V
-
mA
-
mW
VDDA
IDDA
analog supply voltage
analog supply current
AOSL1 and AOSL0 = 0
CVBS mode
3.15
3.3
-
47
3.45
V
-
mA
Y/C mode
-
72
-
mA
PA
power dissipation analog CVBS mode
part
Y/C mode
-
150
-
mW
-
240
-
mW
Ptot(A+D)
total power dissipation
analog and digital part
CVBS mode
Y/C mode
[1] -
450
-
mW
[1] -
540
-
mW
Ptot(A+D)(pd) total power dissipation CE pulled down to ground
-
5
-
mW
analog and digital part in
Power-down mode
Ptot(A+D)(ps)
total power dissipation
I2C-bus controlled via
-
75
-
mW
analog and digital part in address 88h = 0Fh
Power-save mode
Analog part
Iclamp
clamping current
VI = 0.9 V DC
-
±8
-
µA
Vi(p-p)
input voltage
for normal video levels
-
0.7
-
V
(peak-to-peak value)
1 V (p-p), −3 dB
termination 27/47 Ω and
AC coupling required;
coupling
capacitor = 22 nF
Zi
input impedance
Ci
input capacitance
αcs
channel crosstalk
9-bit analog-to-digital converters
clamping current off
fi < 5 MHz
200
-
-
-
-
-
-
kΩ
10
pF
−50
dB
B
analog bandwidth
at −3 dB
-
7
-
MHz
φdiff
differential phase
amplifier plus anti-alias
-
2
-
deg
filter bypassed
Gdiff
differential gain
amplifier plus anti-alias
-
2
-
%
filter bypassed
fclk(ADC)
LEdc(d)
ADC clock frequency
DC differential linearity
error
12.8
-
-
0.7
14.3
MHz
-
LSB
LEdc(i)
DC integral linearity error
-
1
-
LSB
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
184 of 208
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