SAA7108AE Datasheet, PDF (137/208 Pages) NXP Semiconductors – HD-CODEC

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Table 141. I²C-bus receiver/transmitter overview …continued
Register function
Subaddress D7
D6
D5
D4
D3
D2
D1
D0
Luminance brightness control
D4h
BRIG7
BRIG6
BRIG5
BRIG4
BRIG3
BRIG2
BRIG1
BRIG0
Luminance contrast control
D5h
CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0
Chrominance saturation control
D6h
SATN7
SATN6
SATN5
SATN4
SATN3
SATN2
SATN1
SATN0
Reserved
D7h
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Horizontal phase scaling
Horizontal luminance scaling increment D8h
XSCY7 XSCY6 XSCY5 XSCY4 XSCY3 XSCY2 XSCY1 XSCY0
D9h
[1]
[1]
[1]
XSCY12 XSCY11 XSCY10 XSCY9 XSCY8
Horizontal luminance phase offset
DAh
XPHY7 XPHY6 XPHY5 XPHY4 XPHY3 XPHY2 XPHY1 XPHY0
Reserved
DBh
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Horizontal chrominance scaling increment DCh
XSCC7 XSCC6 XSCC5 XSCC4 XSCC3 XSCC2 XSCC1 XSCC0
DDh
[1]
[1]
[1]
XSCC12 XSCC11 XSCC10 XSCC9 XSCC8
Horizontal chrominance phase offset
DEh
XPHC7 XPHC6 XPHC5 XPHC4 XPHC3 XPHC2 XPHC1 XPHC0
Reserved
DFh
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Vertical scaling
Vertical luminance scaling increment
E0h
YSCY7 YSCY6 YSCY5 YSCY4 YSCY3 YSCY2 YSCY1 YSCY0
E1h
YSCY15 YSCY14 YSCY13 YSCY12 YSCY11 YSCY10 YSCY9 YSCY8
Vertical chrominance scaling increment E2h
YSCC7 YSCC6 YSCC5 YSCC4 YSCC3 YSCC2 YSCC1 YSCC0
E3h
YSCC15 YSCC14 YSCC13 YSCC12 YSCC11 YSCC10 YSCC9 YSCC8
Vertical scaling mode control
E4h
[1]
[1]
[1]
YMIR
[1]
[1]
[1]
YMODE
Reserved
E5h to E7h ^[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Vertical chrominance phase offset ‘00’
E8h
YPC07 YPC06 YPC05 YPC04 YPC03 YPC02 YPC01 YPC00
Vertical chrominance phase offset ‘01’
E9h
YPC17 YPC16 YPC15 YPC14 YPC13 YPC12 YPC11 YPC10
Vertical chrominance phase offset ‘10’
EAh
YPC27 YPC26 YPC25 YPC24 YPC23 YPC22 YPC21 YPC20
Vertical chrominance phase offset ‘11’
EBh
YPC37 YPC36 YPC35 YPC34 YPC33 YPC32 YPC31 YPC30
Vertical luminance phase offset ‘00’
ECh
YPY07
YPY06
YPY05
YPY04
YPY03
YPY02
YPY01
YPY00
Vertical luminance phase offset ‘01’
EDh
YPY17
YPY16
YPY15
YPY14
YPY13
YPY12
YPY11
YPY10
Vertical luminance phase offset ‘10’
EEh
YPY27
YPY26
YPY25
YPY24
YPY23
YPY22
YPY21
YPY20
Vertical luminance phase offset ‘11’
EFh
YPY37
YPY36
YPY35
YPY34
YPY33
YPY32
YPY31
YPY30
[1] All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements.