SAA7108AE Datasheet, PDF (74/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Luminance and chrominance scale increments (XSCY[12:0] A9h[4:0] A8h[7:0] and
XSCC[12:0] ADh[4:0] ACh[7:0]) are defined independently, but must be set in a 2 : 1
relationship in the actual data path implementation. The phase offsets XPHY[7:0]
AAh[7:0] and XPHC[7:0] AEh[7:0] can be used to shift the sample phases slightly.
XPHY[7:0] and XPHC[7:0] covers the phase offset range 7.999T to ¹â„₃₂T. The phase
offsets should also be programmed in a 2 : 1 ratio.
The underlying phase controlling DTO has a 13-bit resolution.
According to the equations:
XSCY [12:0] = 1024 × -_X----^NP----_Sp---_Ci--^x---_[^_--₅--ⁱ-_:-ⁿ-₀----_] × -_N----_p---_i--_x-¹--_{_}----_o---_u----_t and XSCC[12:0] = -^X----^S---^C----^Y---₂--^[--¹---²---^:--⁰----^]
the VPD covers the scale range from 0.125 to zoom 3.5. VPD acts equivalent to a
polyphase filter with 64 possible phases. In combination with the prescaler, it is possible to
get very accurate samples from a highly anti-aliased integer downscaled input picture.
9.3.3 Vertical scaling
The vertical scaler of the SAA7108AE; SAA7109AE decoder part consists of a line FIFO
buffer for line repetition and the vertical scaler block, which implements the vertical scaling
on the input data stream in 2 different operational modes from theoretical zoom by 64
down to icon size ¹â„₆₄. The vertical scaler is located between the BCS and horizontal fine
scaler, so that the BCS can be used to compensate the DC gain amplification of the ACM
mode (see Section 9.3.3.2) as the internal RAMs are only 8-bit wide.
9.3.3.1 Line FIFO buffer (subaddresses 91h, B4h and C1h, E4h)
The line FIFO buffer is a dual ported RAM structure for 768 pixels, with asynchronous
write and read access. The line buffer can be used for various functions, but not all
functions may be available simultaneously.
The line buffer can buffer a complete unscaled active video line or more than one shorter
lines (only for non-mirror mode), for selective repetition for vertical zoom-up.
For zooming up 240 lines to 288 lines e.g., every fourth line is requested (read) twice from
the vertical scaling circuitry for calculation.
For conversion of a 4 : 2 : 0 or 4 : 1 : 0 input sampling scheme (MPEG, video phone,
Indeo YUV-9) to ITU like sampling scheme 4 : 2 : 2, the chrominance line buffer is read
twice or four times, before being refilled again by the source. It has to be preserved by
means of the input acquisition window definition, so that the processing starts with a line
containing luminance and chrominance information for 4 : 2 : 0 and 4 : 1 : 0 input. The bits
FSC[2:1] 91h[2:1] define the distance between the Y/C lines. In the event of 4 : 2 : 2 and
4 : 1 : 1 FSC2 and FSC1 have to be set to ‘00’.
The line buffer can also be used for mirroring, i.e. for flipping the image left to right, for the
vanity picture in video phone applications (bit YMIR[B4h[4]]). In mirror mode only one
active prescaled line can be held in the FIFO at a time.
The line buffer can be utilized as an excessive pipeline buffer for discontinuous and
variable rate transfer conditions at the expansion port or image port.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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