SAA7108AE Datasheet, PDF (61/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
ITU counting
525 1
2
3
4
5
6
7
8
9
10
...
21
22
single field counting 262 1
2
3
4
5
6
7
8
9
10
...
21
22
CVBS
HREF
F_ITU656
V123⁽¹⁾
VGATE
FID
VSTO[8:0] = 101h
(a) 1st field
VSTA[8:0] = 011h
ITU counting
262 263 264 265 266 267 268 269 270 271 272 . . . 284 285
single field counting 262 263 1
2
3
4
5
6
7
8
9
. . . 21 22
CVBS
HREF
F_ITU656
V123⁽¹⁾
VGATE
VSTO[8:0] = 101h
FID
(b) 2nd field
VSTA[8:0] = 011h
mhb541
(1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during the falling
edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field is EVEN. The specific
position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to
version.
The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to Table 21.
For further information see Table 160, Table 161 and Table 162.
Fig 34. Vertical timing diagram for 60 Hz/525 line systems
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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