SAA7108AE Datasheet, PDF (131/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 139. Description of I²C-bus format^[1]
Code
Description
S
START condition
Sr
repeated START condition
SLAVE
ADDRESS W
0100 0010 (42h, default) or 0100 0000 (40h)^[2]
SLAVE
ADDRESS R
0100 0011 (43h, default) or 0100 0001 (41h)^[2]
ACK-s
acknowledge generated by the slave
ACK-m
acknowledge generated by the master
SUBADDRESS subaddress byte; see Table 140 and Table 141
DATA
data byte; see Table 141; if more than one byte DATA is transmitted the
subaddress pointer is automatically incremented
P
STOP condition
[1] The SAA7108AE; SAA7109AE supports the ‘fast mode’ I²C-bus specification extension (data rate up to
400 kbit/s).
[2] If pin RTCO is strapped to V_DDD via a 3.3 kΩ resistor.
Table 140. Subaddress description and access
Subaddress
Description
00h
chip version
F0h to FFh
reserved
Video decoder: 01h to 2Fh
01h to 05h
front-end part
06h to 19h
decoder part
1Ah to 1Eh
reserved
1Fh
video decoder status byte
20h to 2Fh
reserved
Audio clock generation: 30h to 3Fh
30h to 3Ah
audio clock generator
3Bh to 3Fh
reserved
General purpose VBI data slicer: 40h to 7Fh
40h to 5Eh
VBI data slicer
5Fh
reserved
60h to 62h
VBI data slicer status
63h to 7Fh
reserved
X port, I port and the scaler: 80h to EFh
80h to 8Fh
task independent global settings
90h to BFh
task A definition
C0h to EFh
task B definition
Access (read/write)
read only
-
read and write
read and write
-
read only
-
read and write
-
read and write
-
read only
-
read and write
read and write
read and write
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
131 of 208