SAA7108AE Datasheet, PDF (113/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 68. CCR and blanking level VBI register, subaddress 5Fh, bit description
Bit
Symbol Access Value Description
7 and 6 CCRS[1:0] R/W
select cross-color reduction filter in luminance; for overall
transfer characteristic of luminance see Figure 9
00 no cross-color reduction
01 cross-color reduction #1 active
10 cross-color reduction #2 active
11 cross-color reduction #3 active
5 to 0 BLNVB[5:0] R/W -
variable blanking level during vertical blanking interval is
typically identical to value of BLNNL
Table 69. Standard control register, subaddress 61h, bit description
Legend: * = default value after reset.
Bit
Symbol Access Value Description
7
DOWND R/W
digital core
0* in normal operational mode
1
in Sleep mode and is reactivated with an I²C-bus address
6
DOWNA R/W
DACs
0* in normal operational mode
1
in Power-down mode
5
INPI
R/W
PAL switch
0* phase is nominal
1
is inverted compared to nominal if RTCE = 1
4
YGS
R/W
luminance gain for white − black
0
100 IRE
1
92.5 IRE including 7.5 IRE set-up of black
3
-
R/W 0
must be programmed with logic 0 to ensure compatibility
to future enhancements
2
SCBW
R/W
bandwidth for chrominance encoding (for overall transfer
characteristic of chrominance in baseband representation
see Figure 7 and Figure 8)
0
enlarged
1* standard
1
PAL
R/W
encoding
0
NTSC (non-alternating V component)
1
PAL (alternating V component)
0
FISE
R/W
total pixel clocks per line
0
864
1
858
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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