SAA7108AE Datasheet, PDF (119/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 87. Disable TTX line registers, subaddresses 7Eh and 7Fh, bit description^[1]
Subaddress Bit Symbol Access Value Description
7Eh
7 to 0 LINE[12:5] R/W -
individual lines in both fields (PAL counting)
7Fh
7 to 0 LINE[20:13] R/W -
can be disabled for insertion of teletext by the
respective bits, disabled line = LINExx (50 Hz
field rate)
[1] This bit mask is effective only if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE.
Table 88. Pixel clock 0, 1 and 2 registers, subaddresses 81h to 83h, bit description
Subaddress Bit Symbol Access Value
Description
81h
7 to 0 PCL[07:00] R/W
82h
7 to 0 PCL[15:08]
83h
7 to 0 PCL[23:16]
defines the frequency of the synthesized
pixel clock PIXCLKO;
f _PIXCLK
=


P_--2---C_-2--4-L_--
×
f

X T A L_
×
8
;
f_XTAL = 27 MHz nominal
20 F63Bh 640 × 480 to NTSC M
1B 5A73h 640 × 480 to PAL B/G (as by strapping
pins)
Table 89. Pixel clock control register, subaddress 84h, bit description
Legend: * = default value after reset.
Bit
Symbol Access Value Description
7
DCLK
R/W 0* set to logic 1
1
set to logic 1
6
PCLSY R/W
pixel clock generator
0* runs free
1
gets synchronized with the vertical sync
5
IFRA
R/W
input FIFO gets reset
0
explicitly at falling edge
1* every field
4
IFBP
R/W
input FIFO
0
active
1* bypassed
3 and 2 PCLE[1:0] R/W
controls the divider for the external pixel clock
00 divider ratio for PIXCLK output is 1
01* divider ratio for PIXCLK output is 2
10 divider ratio for PIXCLK output is 4
11 divider ratio for PIXCLK output is 8
1 and 0 PCLI[1:0] R/W
controls the divider for the internal pixel clock
00 divider ratio for internal PIXCLK is 1
01* divider ratio for internal PIXCLK is 2
10 divider ratio for internal PIXCLK is 4
11 not allowed
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
119 of 208