SAA7108AE Datasheet, PDF (154/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
11.2.3 Programming register audio clock generation
See equations in Section 9.6 and examples in Table 35 and Table 36.
11.2.3.1 Subaddresses 30h to 32h
Table 170. Audio master clock (AMCLK) cycles per field
Subaddress Control bits 7 to 0
30h
ACPF7 ACPF6 ACPF5 ACPF4 ACPF3 ACPF2 ACPF1 ACPF0
31h
ACPF15 ACPF14 ACPF13 ACPF12 ACPF11 ACPF10 ACPF9 ACPF8
32h
-
-
-
-
-
-
ACPF17 ACPF16
11.2.3.2 Subaddresses 34h to 36h
Table 171. Audio master clock (AMCLK) nominal increment
Subaddress Control bits 7 to 0
34h
ACNI7 ACNI6 ACNI5 ACNI4 ACNI3
35h
ACNI15 ACNI14 ACNI13 ACNI12 ACNI11
36h
-
-
ACNI21 ACNI20 ACNI19
ACNI2
ACNI10
ACNI18
ACNI1
ACNI9
ACNI17
ACNI0
ACNI8
ACNI16
11.2.3.3 Subaddress 38h
Table 172. Clock ratio audio master clock (AMXCLK) to serial bit clock (ASCLK)
Subaddress Control bits 7 to 0
38h
-
-
SDIV5 SDIV4 SDIV3 SDIV2 SDIV1
SDIV0
11.2.3.4 Subaddress 39h
Table 173. Clock ratio serial bit clock (ASCLK) to channel select clock (ALRCLK)
Subaddress Control bits 7 to 0
39h
-
-
LRDIV5 LRDIV4 LRDIV3 LRDIV2 LRDIV1 LRDIV0
11.2.3.5 Subaddress 3Ah
Table 174. Audio clock control; 3Ah[3:0]
Bit Description
Symbol Value Function
3 audio PLL modes APLL 0
PLL active, AMCLK is field-locked
1
PLL open, AMCLK is free-running
2 audio master clock AMVR 0
vertical reference
vertical reference pulse is taken from internal
decoder
1
vertical reference is taken from XRV input
(expansion port)
1 ALRCLK phase LRPH 0
ALRCLK edges triggered by falling edges of ASCLK
1
ALRCLK edges triggered by rising edges of ASCLK
0 ASCLK phase
SCPH 0
ASCLK edges triggered by falling edges of AMCLK
1
ASCLK edges triggered by rising edges of AMCLK
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
154 of 208