SAA7108AE Datasheet, PDF (153/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
11.2.2.26 Subaddress 19h
Table 168. Raw data offset control; RAWO[7:0] 19h[7:0]; see Figure 28
Offset
Control bits 7 to 0
RAWO7 RAWO6 RAWO5 RAWO4 RAWO3 RAWO2 RAWO1 RAWO0
−128 LSB
0
0
0
0
0
0
0
0
0 LSB
1
0
0
0
0
0
0
0
+128 LSB
1
1
1
1
1
1
1
1
11.2.2.27 Subaddress 1Fh
Table 169. Status byte video decoder; 1Fh[7:0]; read only register
Bit Description
I²C-bus OLDSB Value Function
control bit 14h[2]
7
status bit for interlace detection
INTL
-
0
non-interlaced
1
interlaced
6
status bit for horizontal and vertical loop HLVLN 0
0
both loops
locked
1
unlocked
status bit for locked horizontal frequency HLCK
1
0
locked
1
unlocked
5
identification bit for detected field
frequency
FIDT
-
0
50 Hz
1
60 Hz
4
gain value for active luminance channel GLIMT -
is limited; maximum (top)
0
not active
1
active
3
gain value for active luminance channel GLIMB -
is limited; minimum (bottom)
0
not active
1
active
2
white peak loop is activated
WIPA
-
0
not active
1
active
1
copy protected source detected
COPRO 0
according to Macrovision version up to
7.01
0
not active
1
active
slow time constant active in WIPA mode SLTCA 1
0
not active
1
active
0
ready for capture (all internal loops
locked)
RDCAP 0
0
not active
1
active
color signal in accordance with selected CODE
1
standard has been detected
0
not active
1
active
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
153 of 208