SAA7108AE Datasheet, PDF (172/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
11.2.5.12 Subaddresses B0h to BFh
Table 227. Vertical luminance scaling increment; register set A [B0h[7:0]; B1h[7:0]] and
B [E0h[7:0]; E1h[7:0]]
Vertical luminance scaling
increment
Control bits
A [B1h[7:4]]
B [E1h[7:4]]
A [B1h[3:0]]
B [E1h[3:0]]
A [B0h[7:4]]
B [E0h[7:4]]
A [B0h[3:0]]
B [E0h[3:0]]
YSCY[15:12] YSCY[11:8] YSCY[7:4] YSCY[3:0]
Scale = ¹⁰²⁴⁄₁ (theoretical) zoom
Scale = ¹⁰²⁴⁄₁₀₂₃ zoom
Scale = 1, equals 1024
0000
0000
0000
0000
0011
0100
0000
1111
0000
0001
1111
0000
Scale = ¹⁰²⁴⁄₁₀₂₅ downscale
Scale = ¹â„_63.999 downscale
0000
1111
0100
1111
0000
1111
0001
1111
Table 228. Vertical chrominance scaling increment; register set A [B2h[7:0]; B3h[7:0]] and
B [E2h[7:0]; E3h[7:0]]
Vertical chrominance scaling
increment
Control bits
A [B3h[7:4]]
B [E3h[7:4]]
A [B3h[3:0]]
B [E3h[3:0]]
A [B2h[7:4]]
B [E2h[7:4]]
A [B2h[3:0]]
B [E2h[3:0]]
YSCC[15:12] YSCC[11:8] YSCC[7:4] YSCC[3:0]
This value must be set to the
luminance value YSCY[15:0]
0000
1111
0000
1111
0000
1111
0001
1111
Table 229. Vertical scaling mode control; register set A [B4h[4 and 0]] and
B [E4h[4 and 0]]^[1]
Vertical scaling mode control
Control bits 4 and 0
YMIR
YMODE
Vertical scaling performs linear interpolation between lines
X
0
Vertical scaling performs higher order accumulating interpolation, X
1
better alias suppression
No mirroring
0
X
Lines are mirrored
1
X
[1] X = don’t care.
Table 230. Vertical chrominance phase offset ‘00’; register set A [B8h[7:0]] and B [E8h[7:0]]
Vertical chrominance Control bits 7 to 0
phase offset
YPC07 YPC06 YPC05 YPC04 YPC03 YPC02 YPC01 YPC00
Offset = 0
0
0
0
0
0
0
0
0
Offset = ³²â„₃₂ = 1 line
0
0
1
0
0
0
0
0
Offset = ²⁵⁵⁄₃₂ lines
1
1
1
1
1
1
1
1
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
172 of 208