SAA7108AE Datasheet, PDF (88/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
10.1 Analog terminals
The SAA7108AE; SAA7109AE has 6 analog inputs AI21 to AI24, AI11 and AI12 (see
Table 38) for composite video CVBS or S-video Y/C signal pairs. Additionally, there are
two differential reference inputs, which must be connected to ground via a capacitor
equivalent to the decoupling capacitors at the 6 inputs. There are no peripheral
components required other than these decoupling capacitors and 18 Ω/56 Ω termination
resistors, one set per connected input signal; see also application example in Figure 68.
Two anti-alias filters are integrated, and self adjusting via the clock frequency.
Clamp and gain control for the two ADCs are also integrated. An analog video output
(pin AOUT) is provided for testing purposes.
Table 38. Analog pin description
Symbol
Pin
I/O Description
Bit
AI24 to AI21 P6, P7, P9 I analog video signal inputs, e.g. 2 CVBS signals and MODE3 to
and P10
two Y/C pairs can be connected simultaneously
MODE0
AI12 and
AI11
P11 and
P13
I analog video signal inputs, e.g. 2 CVBS signals and MODE3 to
two Y/C pairs can be connected simultaneously
MODE0
AOUT
M10
O analog video output, for test purposes
AOSL1 and
AOSL0
AI1D and
AI2D
P12 and
P8
I analog reference pins for differential ADC operation -
10.2 Audio clock signals
The SAA7108AE; SAA7109AE also synchronizes the audio clock and sampling rate to the
video frame rate, via a very slow PLL. This ensures that the multimedia capture and
compression processes always gather the same predefined number of samples per video
frame.
An audio master clock AMCLK and two divided clocks, ASCLK and ALRCLK, are
generated; see Table 39.
• ASCLK: can be used as audio serial clock
• ALRCLK: audio left/right channel clock
The ratios are programmable; see Section 9.6.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
88 of 208