SAA7108AE Datasheet, PDF (15/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 4.
Symbol
V_SSAd
AGND
V_DDAd
V_SSAd
V_SSAd
CE
XTALId
XTALOd
XTOUTd
V_SSXd
AI24
AI23
AI2D
AI22
AI21
AI12
AI1D
AI11
Pin description …continued
Pin
Type^[1]
N9
S
N10
S
N11
S
N12
S
N13
S
N14
I
P2
I
P3
O
P4
O
P5
S
P6
I
P7
I
P8
I
P9
I
P10
I
P11
I
P12
I
P13
I
Description
analog ground (decoder)
analog ground (decoder) connected to substrate
3.3 V analog supply voltage (decoder)
analog ground (decoder)
analog ground (decoder)
chip enable or reset input (with internal pull-up)
27 MHz crystal input (decoder)
27 MHz crystal output (decoder)
crystal oscillator output signal (decoder); auxiliary signal
ground for crystal oscillator (decoder)
analog input 24
analog input 23
differential analog input for channel 2; connect to ground via a capacitor
analog input 22
analog input 21
analog input 12
differential analog input for channel 1; connect to ground via a capacitor
analog input 11
[1] Pin type: I = input, O = output, S = supply, pu = pull-up.
[2] For board design without boundary scan implementation connect TRSTe and TRSTd to ground.
[3] This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRSTe and TRSTd can be used to force the Test Access
Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once.
[4] In accordance with the “IEEE1149.1” standard the pins TDIe (TDId), TMSe (TMSd), TCKe (TCKd) and TRSTe (TRSTd) are input pins
with an internal pull-up resistor and TDOe (TDOd) is a 3-state output pin.
[5] Pin strapping is done by connecting the pin to supply via a 3.3 kΩ resistor. During the power-up reset sequence the corresponding pins
are switched to input mode to read the strapping level. For the default setting no strapping resistor is necessary (internal pull-down).
[6] Pin ALRCLK = LOW for 24.576 MHz crystal (default); pin ALRCLK = HIGH for 32.110 MHz crystal.
[7] Pin RTCO operates as I²C-bus slave address pin; pin RTCO = LOW for slave address 42h/43h (default); pin RTCO = HIGH for slave
address 40h/41h.
8. Functional description of digital video encoder part
The digital video encoder part encodes digital luminance and color difference signals
(C_B-Y-C_R) or digital RGB signals into analog CVBS, S-video and, optionally, RGB or
C_R-Y-C_B signals. NTSC M, PAL B/G and sub-standards are supported.
The SAA7108AE; SAA7109AE can be directly connected to a PC video graphics
controller with a maximum resolution of 1280 × 1024 (progressive) or 1920 × 1080
(interlaced) at a 50 Hz or 60 Hz frame rate. A programmable scaler scales the computer
graphics picture so that it will fit into a standard TV screen with an adjustable underscan
area. Non-interlaced-to-interlaced conversion is optimized with an adjustable anti-flicker
filter for a flicker-free display at a very high sharpness.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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