SAA7108AE Datasheet, PDF (186/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 240. Characteristics of the digital video decoder part …continued
V_DDD = 3.0 V to 3.6 V; V_DDA = 3.1 V to 3.5 V; T_amb = 0 °C to 70 °C (typical values measured at T_amb = 25 °C); timings and
levels refer to drawings and conditions illustrated in Figure 67; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Subcarrier PLL
f_sc(nom)
nominal subcarrier
frequency
PAL BGHI
NTSC M
-
4433619 -
Hz
-
3579545 -
Hz
PAL M
-
3575612 -
Hz
PAL N
-
3582056 -
Hz
∆f_sc
lock-in range
Crystal oscillator for 32.11 MHz^[4]
±400
-
-
Hz
f_xtal(nom)
∆f/f_xtal(nom)
nominal crystal frequency 3rd harmonic
nominal crystal frequency
deviation
-
32.11
−70 × 10^−6 -
-
MHz
+70 × 10^−6
∆f/f_xtal(nom)(T)
nominal crystal frequency
deviation with
temperature
−30 × 10^−6 -
+30 × 10^−6
Crystal specification (X1)
T_amb(X1)
ambient temperature
C_L
load capacitance
R_s
series resonance resistor
C₁
motional capacitance
C₀
parallel capacitance
Crystal oscillator for 24.576 MHz^[4]
0
-
70
°C
8
-
-
pF
-
40
80
Ω
-
1.5 ± 20 % -
fF
-
4.3 ± 20 % -
pF
f_xtal(nom)
∆f/f_xtal(nom)
nominal crystal frequency 3rd harmonic
nominal crystal frequency
deviation
-
24.576
−50 × 10^−6 -
-
MHz
+50 × 10^−6
∆f/f_xtal(nom)(T)
nominal crystal frequency
deviation with
temperature
−20 × 10^−6 -
+20 × 10^−6
Crystal specification (X1)
T_amb(X1)
ambient temperature
C_L
load capacitance
R_s
series resonance resistor
C₁
motional capacitance
C₀
parallel capacitance
Clock input timing (XCLK)
0
-
70
°C
8
-
-
pF
-
40
80
Ω
-
1.5 ± 20 % -
fF
-
3.5 ± 20 % -
pF
T_cy
cycle time
31
-
45
ns
δ
duty factor for t_LLCH/t_LLC
40
50
60
%
t_r
rise time
-
-
5
ns
t_f
fall time
-
-
5
ns
Data and control signal input timing X port, related to XCLK input
t_SU;DAT
t_HD;DAT
input data setup time
input data hold time
-
10
-
ns
-
3
-
ns
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
186 of 208