SAA7108AE Datasheet, PDF (197/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
The digital output signals in front of the DACs under nominal (nominal here stands for the
settings given in Table 66 to Table 73 for example a standard PAL or NTSC signal)
conditions occupy different conversion ranges, as indicated in Table 241 for a ¹⁰⁰⁄₁₀₀ color
bar signal.
By setting the reference currents of the DACs as shown in Table 241, standard compliant
amplitudes can be achieved for all signal combinations; it is assumed that in
subaddress 16h, parameter DACF = 0000b, that means the fine adjustment for all DACs
in common is set to 0 %.
If S-video output is desired, the adjustment for the C (chrominance subcarrier) output
should be identical to the one for VBS (luminance plus sync) output.
Table 241. Digital output signals conversion range
Set/out
CVBS, sync tip-to-white
VBS, sync tip-to-white
Digital settings see Table 66 to Table 73
see Table 66 to Table 73
Digital output
1 014
881
Analog settings e.g. B DAC = 1Fh
e.g. G DAC = 1Bh
Analog output
1.23 V (p-p)
1.00 V (p-p)
RGB, black-to-white
see Table 61
876
e.g. R DAC = G DAC = B DAC = 0Bh
0.70 V (p-p)
17.3 Suggestions for a board layout
Use separate ground planes for analog and digital ground. Connect these planes only at
one point directly under the device, by using a 0 Ω resistor directly at the supply stage.
Use separate supply lines for the analog and digital supply. Place the supply decoupling
capacitors close to the supply pins.
Use L_bead (ferrite coil) in each digital supply line close to the decoupling capacitors to
minimize radiation energy (EMC).
Place the analog coupling (clamp) capacitors close to the analog input pins. Place the
analog termination resistors close to the coupling capacitors.
Be careful of hidden layout capacitors around the crystal application.
Use serial resistors in clock, sync and data lines, to avoid clock or data reflection effects
and to soften data energy.
The SAA7108AE; SAA7109AE crystal temperature depends on the PCB it is soldered on.
For normal airflow conditions at a maximum ambient temperature of 70 °C it will be
sufficient to provide:
• PCB dimensions at least 2000 mm²
• PCB at least 4 layers
• At least 50 vias (connecting PCB layers) close to the chip
• Metal coverage at least 60 % on at least 2 PCB layers near the chip
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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