SAA7108AE Datasheet, PDF (140/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
AI24
AI23
AD2
AI22
AI21
AI24
AI23
AD2
CHROMA AI22
AI21
CHROMA
AI12
AD1
AI11
LUMA
mhb561
AI12
AI11
AD1
LUMA
mhb562
Fig 55. Mode 2 CVBS (automatic gain)
Fig 56. Mode 3 CVBS (automatic gain)
AI24
AI23
AI22
AD2
AI21
AI24
CHROMA
AI23
AI22
AD2
AI21
CHROMA
AI12
AD1
AI11
LUMA
mhb563
AI12
AI11
AD1
LUMA
mhb564
Fig 57. Mode 4 CVBS (automatic gain)
Fig 58. Mode 5 CVBS (automatic gain)
AI24
AI23
AD2
AI22
AI21
AI24
AI23
AD2
CHROMA AI22
AI21
CHROMA
AI12
AD1
AI11
LUMA
mhb565
I²C-bus bit BYPS (subaddress 09h,
bit D7) should be set to logic 1 (full
luminance bandwidth).
Fig 59. Mode 6 Y + C (gain channel 2
adjusted via GAI2)
AI12
AD1
AI11
LUMA
mhb566
I²C-bus bit BYPS (subaddress 09h,
bit D7) should be set to logic 1 (full
luminance bandwidth).
Fig 60. Mode 7 Y + C (gain channel 2
adjusted via GAI2)
AI24
AI23
AD2
AI22
AI21
AI24
AI23
AD2
CHROMA AI22
AI21
CHROMA
AI12
AD1
AI11
LUMA
mhb567
I²C-bus bit BYPS (subaddress 09h,
bit D7) should be set to logic 1 (full
luminance bandwidth).
Fig 61. Mode 8 Y + C (gain channel 2
adapted to Y gain)
AI12
AD1
AI11
LUMA
mhb568
I²C-bus bit BYPS (subaddress 09h,
bit D7) should be set to logic 1 (full
luminance bandwidth).
Fig 62. Mode 9 Y + C (gain channel 2
adapted to Y gain)
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
140 of 208