SAA7108AE Datasheet, PDF (82/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
9.5.3 Text FIFO
The data of the internal VBI data slicer is collected in the text FIFO before the
transmission over the I port is requested (normally before the video window starts). It is
partitioned into two FIFO sections. A complete line is filled into the FIFO before a data
transfer is requested. So normally, one line of text data is ready for transfer, while the next
text line is collected. Thus sliced text data is delivered as a block of qualified data, without
any qualification gaps in the byte stream of the I port.
The decoded VBI data is collected in the dedicated VBI data FIFO. After the capture of a
line has been completed, the FIFO can be streamed through the image port, preceded by
a header, giving line number and standard.
The VBI data period can be signalled via the sliced data flag on pin IGP0 or IGP1. The
decoded VBI data is lead by the ITU ancillary data header (DID[5:0] 5Dh[5:0] at value
< 3Eh) or by SAV/EAV codes selectable by DID[5:0] at value 3Eh or 3Fh. Pin IGP0 or
IGP1 is set if the first byte of the ANC header is valid on the I port bus. It is reset if an SAV
occurs. So it may frame multiple lines of text data output, in the event that the video
processing starts with a distance of several video lines to the region of text data. Valid
sliced data from the text FIFO is available on the I port as long as the IGP0 or IGP1 flag is
set and the data qualifier is active on pin IDQ.
The decoded VBI data is presented in two different data formats, controlled by bit
RECODE.
• RECODE = 1: values 00h and FFh will be recoded to even parity values 03h and FCh
• RECODE = 0: values 00h and FFh may occur in the data stream as detected
9.5.4 Video and text arbitration (subaddress 86h)
Sliced text data and scaled video data are transferred over the same bus, the I port. The
mixed transfer is controlled by an arbitration circuit.
If the video data is transferred without any interrupt and the video FIFO does not need to
buffer any output pixel, the text data is inserted after the end of a scaled video line,
normally during the blanking interval of the video.
9.5.5 Data stream coding and reference signal generation (subaddresses 84h,
85h and 93h)
As horizontal and vertical reference signals are logic 1, active gate signals are generated,
which frame the transfer of the valid output data. As an alternative to the gates, the
horizontal and vertical trigger pulses are generated on the rising edges of the gates.
Due to the dynamic FIFO behavior of the complete scaler path, the output signal timing
has no fixed timing relationship to the real-time input video stream. So fixed propagation
delays, in terms of clock cycles, related to the analog input cannot be defined.
The data stream is accompanied by a data qualifier. Additionally invalid data cycles are
marked with code 00h.
If ITU 656 like codes are not required, they can be suppressed in the output stream.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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