SAA7108AE Datasheet, PDF (16/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Besides the most common 16-bit 4 : 2 : 2 C_B-Y-C_R input format (using 8 pins with double
edge clocking), other C_B-Y-C_R and RGB formats are also supported; see Table 12 to
Table 18.
A complete 3 bytes × 256 bytes Look-Up Table (LUT), which can be used, for example, as
a separate gamma corrector, is located in the RGB domain; it can be loaded either
through the video input port Pixel Data (PD) or via the I²C-bus.
The SAA7108AE; SAA7109AE supports a 32-bit × 32-bit × 2-bit hardware cursor, the
pattern of which can also be loaded through the video input port or via the I²C-bus.
It is also possible to encode interlaced 4 : 2 : 2 video signals such as PC-DVD; for that the
anti-flicker filter, and in most cases the scaler, will simply be bypassed.
Besides the applications for video output, the SAA7108AE; SAA7109AE can also be used
for generating a kind of auxiliary VGA output, when the RGB non-interlaced input signal is
fed to the DACs. This may be of interest for example, when the graphics controller
provides a second graphics window at its video output port.
The basic encoder function consists of subcarrier generation, color modulation and
insertion of synchronization signals at a crystal-stable clock rate of 13.5 MHz
(independent of the actual pixel clock used at the input side), corresponding to an internal
4 : 2 : 2 bandwidth in the luminance/color difference domain. Luminance and
chrominance signals are filtered in accordance with the standard requirements of
‘RS-170-A’ and ‘ITU-R BT.470-3’.
For ease of analog post filtering the signals are twice oversampled to 27 MHz before
digital-to-analog conversion.
The total filter transfer characteristics (scaler and anti-flicker filter are not taken into
account) are illustrated in Figure 6 to Figure 11. All three DACs are realized with full 10-bit
resolution. The C_R-Y-C_B to RGB dematrix can be bypassed (optionally) in order to provide
the upsampled C_R-Y-C_B input signals.
The 8-bit multiplexed C_B-Y-C_R formats are ‘ITU-R BT.656’ (D1 format) compatible, but the
SAV and EAV codes can be decoded optionally, when the device is operated in
Slave mode. For assignment of the input data to the rising or falling clock edge
see Table 12 to Table 18.
In order to display interlaced RGB signals through a euro-connector TV set, a separate
digital composite sync signal (pin HSM_CSYNC) can be generated; it can be advanced
up to 31 periods of the 27 MHz crystal clock in order to be adapted to the RGB processing
of a TV set.
The SAA7108AE; SAA7109AE synthesizes all necessary internal signals, color subcarrier
frequency and synchronization signals from that clock.
Wide screen signalling data can be loaded via the I²C-bus and is inserted into line 23 for
standards using a 50 Hz field rate.
VPS data for program dependent automatic start and stop of such featured VCRs is
loadable via the I²C-bus.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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