SAA7108AE Datasheet, PDF (32/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
The second rule is that there has to be data in the buffer FIFO when the encoder enters
the active video area. Therefore, the vertical offset in the input path needs to be a bit
shorter than the offset of the encoder.
The following gives the set of equations required to program the IC for the most common
application: A post processor in Master mode with non-interlaced video input data.
Some variables are defined below:
• InPix: the number of active pixels per input line
• InPpl: the length of the entire input line in pixel clocks
• InLin: the number of active lines per input field/frame
• TPclk: the pixel clock period
• RiePclk: the ratio of internal to external pixel clock
• OutPix: the number of active pixels per output line
• OutLin: the number of active lines per output field
• TXclk: the encoder clock period (37.037 ns)
8.20.1 TV display window
At 60 Hz, the first visible pixel has the index 256, 710 pixels can be encoded; at 50 Hz, the
index is 284, 702 pixels can be visible.
The output lines should be centred on the screen. It should be noted that the encoder has
2 clocks per pixel; see Table 76.
ADWHS = 256 + 710 − OutPix (60 Hz); ADWHS = 284 + 702 − OutPix (50 Hz);
ADWHE = ADWHS + OutPix × 2 (all frequencies)
For vertical, the procedure is the same. At 60 Hz, the first line with video information is
number 19, 240 lines can be active. For 50 Hz, the numbers are 23 and 287;
see Table 84.
FAL = 19 + ²----⁴---⁰----^–-----^O2----^u----^t--^L---ⁱ--ⁿ-- (60 Hz); FAL = 23 + ²----⁸---⁷----^–-----^O2----^u----^t--^L---ⁱ--ⁿ-- (50 Hz);
LAL = FAL + OutLin (all frequencies)
Most TV sets use overscan, and not all pixels are visible. There is no standard for the
factor, it is highly recommended to make the number of output pixels and lines adjustable.
A reasonable underscan factor is 10 %, giving approximately 640 output pixels per line.
8.20.2 Input frame and pixel clock
The total number of pixel clocks per line and the input horizontal offset need to be chosen
next. The only constraint is that the horizontal blanking has at least 10 clock pulses.
The required pixel clock frequency can be determined in the following way: Due to the
limited internal FIFO size, the input path has to provide all pixels in the same time frame
as the encoders vertical active time. The scaler also has to process the first and last
border lines for the anti-flicker function. Thus:
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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