SAA7108AE Datasheet, PDF (26/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
8.13 RGB processor
This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be
fed to a SCART plug.
Before Y, C_B and C_R signals are de-matrixed, individual gain adjustment for Y and color
difference signals and 2 times oversampling for luminance and 4 times oversampling for
color difference signals is performed. The transfer curves of luminance and color
difference components of RGB are illustrated in Figure 10 and Figure 11.
8.14 Triple DAC
Both Y and C signals are converted from digital-to-analog in a 10-bit resolution at the
output of the video encoder. Y and C signals are also combined into a 10-bit CVBS signal.
The CVBS output signal occurs with the same processing delay as the Y, C and optional
RGB or C_R-Y-C_B outputs. Absolute amplitude at the input of the DAC for CVBS is reduced
by ¹⁵⁄₁₆ with respect to Y and C DACs to make maximum use of the conversion ranges.
RED, GREEN and BLUE signals are also converted from digital-to-analog, each providing
a 10-bit resolution.
The reference currents of all three DACs can be adjusted individually in order to adapt for
different output signals. In addition, all reference currents can be adjusted commonly to
compensate for small tolerances of the on-chip band gap reference voltage.
Alternatively, all currents can be switched off to reduce power dissipation.
All three outputs can be used to sense for an external load (usually 75 Ω) during a
pre-defined output. A flag in the I²C-bus status byte reflects whether a load is applied or
not. In addition, an automatic sense mode can be activated which indicates a 75 Ω load at
any of the three outputs at the dedicated interrupt pin TVD.
If the SAA7108AE; SAA7109AE is required to drive a second (auxiliary) VGA monitor or
an HDTV set, the DACs receive the signal coming from the HD data path. In this event,
the DACs are clocked at the incoming PIXCLKI instead of the 27 MHz crystal clock used
in the video encoder.
8.15 HD data path
This data path allows the SAA7108AE; SAA7109AE to be used with VGA or HDTV
monitors. It receives its data directly from the cursor generator and supports RGB and
Y-P_B-P_R output formats (RGB not with Y-P_B-P_R input formats). No scaling is done in this
mode.
A gain adjustment either leads the full level swing to the digital-to-analog converters or
reduces the amplitude by a factor of 0.69. This enables sync pulses to be added to the
signal as it is required for display units expecting signals with sync pulses, either regular or
3-level syncs.
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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