SAA7108AE Datasheet, PDF (161/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 195. I port FIFO flag control and arbitration; global set 86h[3:0]^[1]
I port FIFO flag control and arbitration
Control bits 3 to 0
FFL1 FFL0 FEL1
FAE FIFO flag almost empty level
< 16 double words
X
X
0
< 8 double words
X
X
0
< 4 double words
X
X
1
0 double words
X
X
1
FAF FIFO flag almost full level
≥ 16 double words
0
0
X
≥ 24 double words
0
1
X
≥ 28 double words
1
0
X
32 double words
1
1
X
[1] X = don’t care.
FEL0
0
1
0
1
X
X
X
X
Table 196. I port I/O enable, output clock and gated clock phase control; global set
87h[7:4]^[1]
Output clock and gated clock phase control
Control bits 7 to 4
IPCK3^[2] IPCK2^[2] IPCK1 IPCK0
ICLK default output phase
X
X
0
0
ICLK phase shifted by ¹â„₂ clock cycle ⇒
X
X
0
1
recommended for ICKS1 = 1 and ICKS0 = 0
(subaddress 80h)
ICLK phase shifted by approximately 3 ns
X
X
1
0
ICLK phase shifted by ¹â„₂ clock cycle +
X
X
1
1
approximately 3 ns ⇒ alternatively to setting ‘01’
IDQ = gated clock default output phase
0
0
X
X
IDQ = gated clock phase shifted by ¹â„₂ clock cycle ⇒ 0
1
X
X
recommended for gated clock output
IDQ = gated clock phase shifted by approximately 1
0
X
X
3 ns
IDQ = gated clock phase shifted by ¹â„₂ clock cycle + 1
1
X
X
approximately 3 ns ⇒ alternatively to setting ‘01’
[1] X = don’t care.
[2] IPCK3 and IPCK2 only affects the gated clock (subaddress 80h, bit ICKS2 = 1).
Table 197. I port I/O enable, output clock and gated clock phase control; global set 87h[1:0]
I port I/O enable
Control bits 1 and 0
IPE1
IPE0
I port output is disabled by software
0
0
I port output is enabled by software
0
1
I port output is enabled by pin ITRI at logic 0
1
0
I port output is enabled by pin ITRI at logic 1
1
1
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
161 of 208