SAA7108AE Datasheet, PDF (77/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
unscaled input
field 1
field 2
scaled output,
no phase offset
field 1
field 2
scaled output,
with phase offset
field 1
field 2
scale dependent start offset
mismatched vertical line distances
correct scale dependent position
Fig 40. Basic problem of interlaced vertical scaling (example: downscale ³â„₅)
mhb547
field 1
upper
B
A
field 2
lower
field 1
case UP-UP
field 2
case LO-LO
field 1
case UP-LO
field 2
case LO-UP
C
D
mhb548
Offset = ^{1---03---22---4--} = 32 = 1 line shift
A = ^1-- input line shift = 16
2
B = ^1-- input line shift + ^1-- scale increment = -Y---S---C----Y---[--1---5---:--0---]- + 16
2
2
64
C = ^1-- scale increment + ^{Y----S---C----Y---[--1---5---:--0---]-}
2
64
D = no offset = 0
Fig 41. Derivation of the phase related equations (example: interlace vertical scaling down to ³â„₅, with field
conversion)
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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