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SAA7108AE Datasheet, PDF (126/208 Pages) NXP Semiconductors – HD-CODEC
NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
SAA7108AE_SAA7109AE_3
Product data sheet
Table 121. HD sync trigger state 2 register, subaddress D5h, bit description
Bit
Symbol Description
7 to 4 HLCPT[3:0] state of the HD line type pointer after trigger
3 and 2 HLPPT[1:0] state of the HD pattern pointer after trigger
1 and 0 HLCT[9:8] see Table 120
Table 122. HD sync trigger state 3 register, subaddress D6h, bit description
Bit
Symbol Description
7 to 0 HDCT[7:0] with HDCT[9:8] (see Table 123) state of the HD duration counter after trigger
(counts backwards)
Table 123. HD sync trigger state 4 register, subaddress D7h, bit description
Bit
Symbol Description
7
-
must be programmed with logic 0 to ensure compatibility to future
enhancements
6 to 4 HEPT[2:0] state of the HD event type pointer in the line type array after trigger
3 and 2 -
must be programmed with logic 0 to ensure compatibility to future
enhancements
1 and 0 HDCT[9:8] see Table 122
Table 124. HD sync trigger phase x registers, subaddresses D8h and D9h, bit description
Subaddress Bit Symbol Description
D9h
7 to 4 -
must be programmed with logic 0 to ensure compatibility to
future enhancements
3 to 0 HTX[11:8] horizontal trigger phase for the HD sync engine in pixel clocks
D8h
7 to 0 HTX[7:0]
Table 125. HD sync trigger phase y registers, subaddresses DAh and DBh, bit description
Subaddress Bit
Symbol Description
DBh
7 to 2 -
must be programmed with logic 0 to ensure compatibility to
future enhancements
1 and 0 HTY[9:8] vertical trigger phase for the HD sync engine in input lines
DAh
7 to 0 HTY[7:0]
Table 126. HD output control register, subaddress DCh, bit description
Legend: * = default value after reset.
Bit
Symbol Access Value Description
7 to 4 -
R/W 0
must be programmed with logic 0 to ensure compatibility to
future enhancements
3
HDSYE R/W
HD sync engine
0* off
1
active
2
HDTC R/W
HD output path processes
0* RGB
1
YUV
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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