SAA7108AE Datasheet, PDF (90/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 40. Clock and real-time synchronization signals …continued
Symbol Pin I/O Description
Bit
LLC2
L14 O line-locked pixel clock, nominal 13.5 MHz
-
RTCO
L13 O
real-time control output, transfers real-time status -
information supporting RTC level 3.1 (see
document “How to use Real Time Control (RTC)”,
available on request)
RTS0
K13 O
real-time status information line 0, can be
programmed to carry various real-time
information; see Table 160
RTSE0[3:0] 12h[3:0]
RTS1
L10 O
real-time status information line 1, can be
programmed to carry various real-time
information; see Table 161
RTSE1[3:0] 12h[7:4]
10.4 Video expansion port (X port)
The expansion port is intended for transporting video streams of image data from other
digital video circuits such as MPEG encoder/decoder and video phone codec, to the
image port (I port); see Table 41.
The expansion port consists of two groups of signals/pins:
• 8-bit data, I/O, regular components video Y-C_B-C_R 4 : 2 : 2, i.e. C_B-Y-C_R-Y, byte serial,
exceptionally raw video samples (e.g. ADC test); in input mode the data bus can be
extended to 16-bit by pins HPD7 to HPD0.
• Clock, synchronization and auxiliary signals, accompanying the data stream, I/O
As output, these are direct copies of the decoder signals.
The data transfers through the expansion port represent a single D1 port, with half duplex
mode. The SAV and EAV codes may be inserted optionally for data input (controlled by
bit XCODE[92h[3]]). The input/output direction is switched for complete fields only.
Table 41. Signals dedicated to the expansion port
Symbol Pin
I/O Description
Bit
XPD7 to K2, K3,
I/O X port data: in output mode controlled by OFTS[2:0] 13h[2:0],
XPD0 L1 to L3, M1,
decoder section, data format see Table 42; 91h[7:0] and
M2 and N1
in input mode Y-C_B-C_R 4 : 2 : 2 serial input C1h[7:0]
data or luminance part of a 16-bit
Y-C_B-C_R 4 : 2 : 2 input
XCLK M3
I/O clock at expansion port: if output, then
copy of LLC; as input normally a double
pixel clock of up to 32 MHz or a gated
clock (clock gated with a qualifier)
XCKS[92h[0]]
XDQ M4
I/O data valid flag of the expansion port input -
(qualifier): if output, then decoder
(HREF and VGATE) gate; see Figure 35
XRDY N3
O data request flag = ready to receive, to XRQT[83h[2]]
work with optional buffer in external
device, to prevent internal buffer overflow;
second function: input related task flag
A/B
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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