SAA7108AE Datasheet, PDF (142/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
11.2.2.7 Subaddress 06h
Table 148. Horizontal sync start; 06h[7:0]
Delay time (step
size = 8/LLC)
Control bits 7 to 0
HSB7 HSB6 HSB5 HSB4 HSB3 HSB2
−128...−109 (50 Hz) forbidden (outside available central counter range)
−128...−108 (60 Hz) forbidden (outside available central counter range)
−108 (50 Hz)...
1
0
0
1
0
1
−107 (60 Hz)...
1
0
0
1
0
1
...108 (50 Hz)
0
1
1
0
1
1
...107 (60 Hz)
0
1
1
0
1
0
109...127 (50 Hz)
forbidden (outside available central counter range)
108...127 (60 Hz)
HSB1
0
0
0
1
HSB0
0
1
0
1
11.2.2.8 Subaddress 07h
Table 149. Horizontal sync stop; 07h[7:0]
Delay time (step
size = 8/LLC)
Control bits 7 to 0
HSS7 HSS6 HSS5 HSS4 HSS3 HSS2
−128...−109 (50 Hz) forbidden (outside available central counter range)
−128...−108 (60 Hz) forbidden (outside available central counter range)
−108 (50 Hz)...
1
0
0
1
0
1
−107 (60 Hz)...
1
0
0
1
0
1
...108 (50 Hz)
0
1
1
0
1
1
...107 (60 Hz)
0
1
1
0
1
0
109...127 (50 Hz)
forbidden (outside available central counter range)
108...127 (60 Hz)
forbidden (outside available central counter range)
HSS1
0
0
0
1
HSS0
0
1
0
1
11.2.2.9 Subaddress 08h
Table 150. Sync control; 08h[7:0]
Bit
Description
Symbol
7
automatic field
AUFD
detection
Value
0
1
6
field selection;
FSEL
0
active if AUFD = 0
1
5
forced ODD/EVEN FOET 0
toggle
1
Function
field state directly controlled via FSEL
automatic field detection; recommended
setting
50 Hz, 625 lines
60 Hz, 525 lines
ODD/EVEN signal toggles only with
interlaced source
ODD/EVEN signal toggles fieldwise even if
source is non-interlaced
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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