SAA7108AE Datasheet, PDF (13/208 Pages) NXP Semiconductors – HD-CODEC

NXP Semiconductors
SAA7108AE; SAA7109AE
HD-CODEC
Table 4.
Symbol
PD3
Pin description …continued
Pin
Type^[1]
F3
I
V_DD(DVO)
V_DDId
TVD
IGPV
IGP0
FSVGC
SDAe
CBO
PIXCLKO
V_DDEd
IGPH
IGP1
ITRI
PD2
F4
S
F11
S
F12
O
F13
O
F14
O
G1
I/O
G2
I/O
G3
O
G4
O
G11 S
G12 O
G13 O
G14 I(/O)
H1
I
PD1
H2
I
PD0
H3
I
V_SSEd
V_SSEd
ICLK
TEST0
IDQ
TEST4
TEST5
TEST3
V_DDId
V_DDId
AMXCLK
ALRCLK
H4
S
H11
S
H12
I/O
H13
O
H14
O
J1
O
J2
I
J3
I
J4
S
J11
S
J12
I
J13
(I/)O
ITRDY
XTRI
XPD7
XPD6
V_SSId
V_SSId
AMCLK
J14
I
K1
I
K2
I/O
K3
I/O
K4
S
K11
S
K12
O
Description
MSB − 4 of encoder input bus with C_B-Y-C_R 4 : 2 : 2; see Table 12 to Table 18 for
pin assignment
digital supply voltage for DVO cells
3.3 V digital supply voltage for core (decoder)
TV detector; hot-plug interrupt pin; HIGH if TV is connected
multi-purpose vertical reference output with IPD output bus
general purpose output signal 0 with IPD output bus
frame synchronization output to VGC (optional input)
serial data input/output (I²C-bus encoder)
composite blanking output to VGC; active LOW
pixel clock output to VGC
3.3 V digital supply voltage for peripheral cells (decoder)
multi-purpose horizontal reference output with IPD output bus
general purpose output signal 1 with IPD output bus
programmable control signals for IPD output bus
MSB − 5 of encoder input bus with C_B-Y-C_R 4 : 2 : 2; see Table 12 to Table 18 for
pin assignment
MSB − 6 of encoder input bus with C_B-Y-C_R 4 : 2 : 2; see Table 12 to Table 18 for
pin assignment
MSB − 7 of encoder input bus with C_B-Y-C_R 4 : 2 : 2; see Table 12 to Table 18 for
pin assignment
digital ground for peripheral cells (decoder)
digital ground for peripheral cells (decoder)
clock for IPD output bus (optional clock input)
scan test output; do not connect
data qualifier for IPD output bus
scan test output; do not connect
scan test input; do not connect
scan test input; do not connect
3.3 V digital supply voltage for core (decoder)
3.3 V digital supply voltage for core (decoder)
audio master external clock input
audio left/right clock output; can be strapped^[5][6] to supply via a 3.3 kΩ resistor
to indicate that the default 24.576 MHz crystal (pin ALRCLK = LOW; internal
pull-down) has been replaced by a 32.110 MHz crystal (pin ALRCLK = HIGH)
target ready input for IPD output bus
control signal for all X port pins
MSB of XPD bus
MSB − 1 of XPD bus
digital ground core (decoder)
digital ground core (decoder)
audio master clock output, must be less than 50 % of crystal clock
SAA7108AE_SAA7109AE_3
Product data sheet
Rev. 03 — 6 February 2007
© NXP B.V. 2007. All rights reserved.
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